Searched full:tsc (Results 1 – 25 of 35) sorted by relevance
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| /Documentation/devicetree/bindings/input/touchscreen/ |
| D | lpc32xx-tsc.txt | 1 * NXP LPC32xx SoC Touchscreen Controller (TSC)
4 - compatible: must be "nxp,lpc3220-tsc"
7 - interrupts: The TSC/ADC interrupt
11 tsc@40048000 {
12 compatible = "nxp,lpc3220-tsc";
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| D | fsl,imx6ul-tsc.yaml | 4 $id: http://devicetree.org/schemas/input/touchscreen/fsl,imx6ul-tsc.yaml#
16 const: fsl,imx6ul-tsc
33 - const: tsc
84 compatible = "fsl,imx6ul-tsc";
90 clock-names = "tsc", "adc";
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| D | ti,am3359-tsc.yaml | 4 $id: http://devicetree.org/schemas/input/touchscreen/ti,am3359-tsc.yaml#
14 const: ti,am3359-tsc
69 tsc {
70 compatible = "ti,am3359-tsc";
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| D | brcm,iproc-touchscreen.txt | 9 - clocks: The clock provided by the SOC to driver the tsc
21 the tsc waits to allow the voltage to settle after
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| D | fsl-mx25-tcq.txt | 28 tsc: tcq@50030400 {
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| /Documentation/virt/kvm/x86/ |
| D | timekeeping.rst | 14 3) TSC Hardware
37 First we discuss the basic hardware devices available. TSC and the related
324 3. TSC Hardware
327 The TSC or time stamp counter is relatively simple in theory; it counts
332 The TSC is represented internally as a 64-bit MSR which can be read with the
334 limitations made it possible to write the TSC, but generally on old hardware it
339 write the TSC MSR is not an architectural guarantee.
341 The TSC is accessible from CPL-0 and conditionally, for CPL > 0 software by
342 means of the CR4.TSD bit, which when enabled, disables CPL > 0 TSC access.
345 atomically not just the TSC, but an indicator which corresponds to the
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| D | hypercalls.rst | 122 __u64 tsc;
130 * tsc: guest TSC value used to calculate sec/nsec pair
134 host and guest. The guest can use the returned TSC value to
137 Returns KVM_EOPNOTSUPP if the host does not use TSC clocksource,
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| D | msr.rst | 92 the tsc value at the current VCPU at the time
94 from current tsc to derive a notion of elapsed time since the
104 tsc-related quantity to nanoseconds
107 shift to be used when converting tsc-related
113 The conversion from tsc to nanoseconds involves an additional
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| /Documentation/virt/hyperv/ |
| D | clocks.rst | 26 also provides access to the virtualized TSC via the RDTSC and
27 related instructions. These TSC instructions do not trap to
29 Hyper-V performs TSC calibration, and provides the TSC frequency
31 in Linux reads this MSR to get the frequency, so it skips TSC
42 value, the guest reads the TSC and then applies the scale and offset
45 to a host with a different TSC frequency, Hyper-V adjusts the
50 support for TSC frequency scaling to enable live migration of VMs
51 across Hyper-V hosts where the TSC frequency may be different.
53 available, it prefers to use Linux's standard TSC-based clocksource.
62 space code performs the same algorithm of reading the TSC and
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| /Documentation/virt/kvm/devices/ |
| D | vcpu.rst | 206 :Parameters: 64-bit unsigned TSC offset
216 Specifies the guest's TSC offset relative to the host's TSC. The guest's
217 TSC is then derived by the following equation:
221 This attribute is useful to adjust the guest's TSC on live migration,
222 so that the TSC counts the time during which the VM was paused. The
227 1. Invoke the KVM_GET_CLOCK ioctl to record the host TSC (tsc_src),
232 guest TSC offset (ofs_src[i]).
235 guest's TSC (freq).
251 5. Invoke the KVM_GET_CLOCK ioctl to record the host TSC (tsc_dest) and
254 6. Adjust the guest TSC offsets for every vCPU to account for (1) time
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| /Documentation/devicetree/bindings/mfd/ |
| D | ti,am3359-tscadc.yaml | 47 tsc:
80 tsc {
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| D | fsl-imx25-tsadc.txt | 1 Freescale MX25 ADC/TSC MultiFunction Device (MFD)
36 tsc: tcq@50030400 {
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| D | maxim,max8925.yaml | 29 maxim,tsc-irq:
115 maxim,tsc-irq = <0>;
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| /Documentation/devicetree/bindings/thermal/ |
| D | rcar-gen3-thermal.yaml | 11 On most R-Car Gen3 and later SoCs, the thermal sensor controllers (TSC)
108 tsc: thermal@e6198000 {
126 thermal-sensors = <&tsc 0>;
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| /Documentation/virt/acrn/ |
| D | cpuid.rst | 46 eax = (Virtual) TSC frequency in kHz.
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| /Documentation/translations/zh_CN/virt/acrn/ |
| D | cpuid.rst | 56 eax = (Virtual) TSC frequency in kHz.
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | nvidia,tegra234-pinmux-common.yaml | 22 i2c1, i2s4, i2s6, aud, spi5, touch, uartj, rsvd1, wdt, tsc,
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| D | brcm,iproc-gpio.txt | 111 tsc {
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| /Documentation/driver-api/hte/ |
| D | tegra-hte.rst | 11 from the system counter TSC which has 31.25MHz clock rate, and the driver
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| /Documentation/devicetree/bindings/timer/ |
| D | nvidia,tegra186-timer.yaml | 15 reference generated by USEC, TSC or either clk_m or OSC. Each TMR can be
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | amlogic,meson-saradc.yaml | 58 Syscon which contains the 5th bit of the TSC (temperature sensor
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| /Documentation/trace/ |
| D | hwlat_detector.rst | 26 for some period, then looking for gaps in the TSC data. Any gap indicates a
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| /Documentation/tools/rtla/ |
| D | rtla-hwnoise.rst | 80 and disabling the TSC watchdog to remove the NMI (it is possible to identify
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| /Documentation/virt/kvm/ |
| D | locking.rst | 263 - tsc offset in vmcb
264 :Comment: 'raw' because updating the tsc offsets must not be preempted.
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| /Documentation/timers/ |
| D | timekeeping.rst | 154 Some hardware (such as the x86 TSC) will cause the sched_clock() function to
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