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Searched full:tx0 (Results 1 – 15 of 15) sorted by relevance

/Documentation/devicetree/bindings/firmware/
Dfsl,scu.yaml61 - description: TX0 MU channel
64 - description: TX0 MU channel
68 - description: TX0 MU channel
77 - description: TX0 MU channel
90 - const: tx0
93 - const: tx0
97 - const: tx0
106 - const: tx0
158 mbox-names = "tx0", "tx1", "tx2", "tx3",
/Documentation/devicetree/bindings/net/can/
Dnxp,sja1000.yaml64 or combination of TX0 and TX1:
65 <0x01> : TX0 invert
66 <0x02> : TX0 pull-down (default)
67 <0x04> : TX0 pull-up
68 <0x06> : TX0 push-pull
/Documentation/devicetree/bindings/net/
Dti,icssg-prueth.yaml35 - const: tx0-0
36 - const: tx0-1
37 - const: tx0-2
38 - const: tx0-3
201 dma-names = "tx0-0", "tx0-1", "tx0-2", "tx0-3",
Dti,k3-am654-cpsw-nuss.yaml97 - const: tx0
271 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
Dintel,ixp4xx-hss.yaml66 description: phandle to the packet TX0, TX1, TX2 and TX3 queues on the NPE
/Documentation/devicetree/bindings/media/
Damphion,vpu.yaml72 - const: tx0
150 mbox-names = "tx0", "tx1", "rx";
161 mbox-names = "tx0", "tx1", "rx";
172 mbox-names = "tx0", "tx1", "rx";
/Documentation/devicetree/bindings/sound/
Dnvidia,tegra30-ahub.txt51 - tx0 .. tx<n>
84 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", "rx3", "tx3";
Dfsl,ssi.yaml81 - description: DMA controller phandle and request line for TX0
92 - const: tx0
Dfsl,spdif.yaml52 - description: Clock for tx0 and rx0.
Drenesas,rz-ssi.yaml67 MID/RID value of SSI tx0 = 0x255
/Documentation/devicetree/bindings/phy/
Dqcom,edp-phy.yaml29 - description: tx0 register block
Dsamsung,ufs-phy.yaml74 - description: symbol clock for output symbol (tx0 symbol clock)
/Documentation/devicetree/bindings/spi/
Domap-spi.yaml116 dma-names = "tx0", "rx0";
/Documentation/driver-api/dmaengine/
Dpxa_dma.rst144 - there are not "acked" transfers (tx0)
185 - allocated queue : tx0
/Documentation/networking/device_drivers/ethernet/ti/
Dcpsw.rst172 // TX queues must be rated starting from 0, so set bws for tx0 and tx1
403 // TX queues must be rated starting from 0, so set bws for tx0 and tx1 for Eth0