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/Documentation/watchdog/
Dwatchdog-kernel-api.rst2 The Linux WatchDog Timer Driver Core kernel API
5 Last reviewed: 12-Feb-2013
10 ------------
11 This document does not describe what a WatchDog Timer (WDT) Driver or Device is.
13 with a WatchDog Timer. If you want to know this then please read the following
14 file: Documentation/watchdog/watchdog-api.rst .
17 WatchDog Timer Drivers that want to use the WatchDog Timer Driver Core
20 a watchdog timer driver then only needs to provide the different routines
21 (operations) that control the watchdog timer (WDT).
24 -------
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Dhpwdt.rst2 HPE iLO NMI Watchdog Driver
11 The HPE iLO NMI Watchdog driver is a kernel module that provides basic
12 watchdog functionality and handler for the iLO "Generate NMI to System"
18 Watchdog functionality is enabled like any other common watchdog driver. That
19 is, an application needs to be started that kicks off the watchdog timer. A
20 basic application exists in tools/testing/selftests/watchdog/ named
21 watchdog-test.c. Simply compile the C file and kick it off. If the system
22 gets into a bad state and hangs, the HPE ProLiant iLO timer register will
29 soft_margin allows the user to set the watchdog timer value.
32 pretimeout allows the user to set the watchdog pretimeout value.
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/Documentation/devicetree/bindings/mfd/
Dbrcm,twd.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom's Timer-Watchdog (aka TWD)
10 - Rafał Miłecki <rafal@milecki.pl>
13 Broadcom has a Timer-Watchdog block used in multiple SoCs (e.g., BCM4908,
15 registers layout). This block consists of: timers, watchdog and optionally a
21 - enum:
22 - brcm,bcm4908-twd
23 - brcm,bcm7038-twd
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/Documentation/devicetree/bindings/watchdog/
Dmarvell,cn10624-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/marvell,cn10624-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell Global Timer (GTI) system watchdog
10 - Bharat Bhushan <bbhushan2@marvell.com>
13 - $ref: watchdog.yaml#
18 - enum:
19 - marvell,cn9670-wdt
20 - marvell,cn10624-wdt
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Dsnps,dw-wdt.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/watchdog/snps,dw-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys Designware Watchdog Timer
10 - Jamie Iles <jamie@jamieiles.com>
13 - $ref: watchdog.yaml#
18 - const: snps,dw-wdt
19 - items:
20 - enum:
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Dnuvoton,npcm-wdt.txt1 Nuvoton NPCM Watchdog
3 Nuvoton NPCM timer module provides five 24-bit timer counters, and a watchdog.
4 The watchdog supports a pre-timeout interrupt that fires 10ms before the
8 - compatible : "nuvoton,npcm750-wdt" for NPCM750 (Poleg), or
9 "nuvoton,wpcm450-wdt" for WPCM450 (Hermon), or
10 "nuvoton,npcm845-wdt" for NPCM845 (Arbel).
11 - reg : Offset and length of the register set for the device.
12 - interrupts : Contain the timer interrupt with flags for
16 - clocks : phandle of timer reference clock.
17 - clock-frequency : The frequency in Hz of the clock that drives the NPCM7xx
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Dcnxt,cx92755-wdt.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/watchdog/cnxt,cx92755-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Conexant Digicolor SoCs Watchdog timer
10 The watchdog functionality in Conexant Digicolor SoCs relies on the so called
12 timer counters. The first timer (called "Timer A") is the only one that can be
13 used as watchdog.
16 - Baruch Siach <baruch@tkos.co.il>
19 - $ref: watchdog.yaml#
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Dqcom-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/qcom-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Krait Processor Sub-system (KPSS) Watchdog timer
10 - Rajendra Nayak <quic_rjendra@quicinc.com>
14 pattern: "^(watchdog|timer)@[0-9a-f]+$"
18 - items:
19 - enum:
20 - qcom,kpss-wdt-ipq4019
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Dxlnx,versal-wwdt.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/xlnx,versal-wwdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Versal window watchdog timer controller
10 - Neeli Srinivas <srinivas.neeli@amd.com>
13 Versal watchdog intellectual property uses window watchdog mode.
14 Window watchdog timer(WWDT) contains closed(first) and open(second)
15 window with 32 bit width. Write to the watchdog timer within
22 - $ref: watchdog.yaml#
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Darm,twd-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/arm,twd-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Timer-Watchdog Watchdog
10 - Rob Herring <robh@kernel.org>
13 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
14 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
15 and watchdog.
17 The TWD is usually attached to a GIC to deliver its two per-processor
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Dti,rti-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/ti,rti-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments K3 SoC Watchdog Timer
10 - Tero Kristo <t-kristo@ti.com>
13 The TI K3 SoC watchdog timer is implemented via the RTI (Real Time
14 Interrupt) IP module. This timer adds a support for windowed watchdog
15 mode, which will signal an error if it is pinged outside the watchdog
21 - $ref: watchdog.yaml#
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Darm,sbsa-gwdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/arm,sbsa-gwdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SBSA (Server Base System Architecture) Generic Watchdog
10 - Fu Wei <fu.wei@linaro.org>
13 The SBSA Generic Watchdog Timer is used to force a reset of the system after
14 two stages of timeout have elapsed. A detailed definition of the watchdog
15 timer can be found in the ARM document: ARM-DEN-0029 - Server Base System
19 - $ref: watchdog.yaml#
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Dbrcm,kona-wdt.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/watchdog/brcm,kona-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom Kona Family Watchdog Timer
10 This watchdog timer is used in the following Broadcom SoCs:
14 - Florian Fainelli <f.fainelli@gmail.com>
15 - Ray Jui <rjui@broadcom.com>
16 - Scott Branden <sbranden@broadcom.com>
19 - $ref: watchdog.yaml#
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Dmpc8xxx-wdt.txt1 * Freescale mpc8xxx watchdog driver (For 83xx, 86xx and 8xx)
4 - compatible: Shall contain one of the following:
6 "fsl,mpc8610-wdt" for an mpc86xx
7 "fsl,mpc823-wdt" for an mpc8xx
8 - reg: base physical address and length of the area hosting the
9 watchdog registers.
10 On the 83xx, "Watchdog Timer Registers" area: <0x200 0x100>
11 On the 86xx, "Watchdog Timer Registers" area: <0xe4000 0x100>
15 - reg: additional physical address and length (4) of location of the
22 WDT: watchdog@0 {
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Dcdns,wdt-r1p2.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/cdns,wdt-r1p2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence watchdog timer controller
10 - Neeli Srinivas <srinivas.neeli@amd.com>
13 The cadence watchdog timer is used to detect and recover from
14 system malfunctions. This watchdog contains 24 bit counter and
19 - $ref: watchdog.yaml#
24 - cdns,wdt-r1p2
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Dti,davinci-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/ti,davinci-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI DaVinci/Keystone Watchdog Timer Controller
10 - Kousik Sanagavarapu <five231003@gmail.com>
13 TI's Watchdog Timer Controller for DaVinci and Keystone Processors.
17 Davinci DM646x - https://www.ti.com/lit/ug/spruer5b/spruer5b.pdf
18 Keystone - https://www.ti.com/lit/ug/sprugv5a/sprugv5a.pdf
21 - $ref: watchdog.yaml#
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Dlinux,wdt-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/linux,wdt-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO-controlled Watchdog
10 - Guenter Roeck <linux@roeck-us.net>
11 - Robert Marko <robert.marko@sartura.hr>
15 const: linux,wdt-gpio
24 - description:
25 Either a high-to-low or a low-to-high transition clears the WDT counter.
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Darmada-37xx-wdt.txt1 * Armada 37xx CPU Watchdog Timer Controller
4 - compatible : must be "marvell,armada-3700-wdt"
5 - reg : base physical address of the controller and length of memory mapped
7 - clocks : the clock feeding the watchdog timer. See clock-bindings.txt
8 - marvell,system-controller : reference to syscon node for the CPU Miscellaneous
13 cpu_misc: system-controller@d000 {
14 compatible = "marvell,armada-3700-cpu-misc", "syscon";
18 wdt: watchdog@8300 {
19 compatible = "marvell,armada-3700-wdt";
21 marvell,system-controller = <&cpu_misc>;
Dxlnx,xps-timebase-wdt.yaml1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/watchdog/xlnx,xps-timebase-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx AXI/PLB softcore and window Watchdog Timer
10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
11 - Srinivas Neeli <srinivas.neeli@amd.com>
14 The Timebase watchdog timer(WDT) is a free-running 32 bit counter.
15 WDT uses a dual-expiration architecture. After one expiration of
22 - $ref: watchdog.yaml#
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Dmediatek,mtk-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/mediatek,mtk-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MediaTek SoCs Watchdog timer
10 - Matthias Brugger <matthias.bgg@gmail.com>
13 The watchdog supports a pre-timeout interrupt that fires
14 timeout-sec/2 before the expiry.
17 - $ref: watchdog.yaml#
22 - enum:
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Dmoxa,moxart-watchdog.txt1 MOXA ART Watchdog timer
5 - compatible : Must be "moxa,moxart-watchdog"
6 - reg : Should contain registers location and length
7 - clocks : Should contain phandle for the clock that drives the counter
11 watchdog: watchdog@98500000 {
12 compatible = "moxa,moxart-watchdog";
/Documentation/devicetree/bindings/timer/
Darm,twd-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,twd-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Timer-Watchdog Timer
10 - Rob Herring <robh@kernel.org>
13 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
14 Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
15 and watchdog.
17 The TWD is usually attached to a GIC to deliver its two per-processor
[all …]
Dnvidia,tegra-timer.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/timer/nvidia,tegra-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra timer
10 - Stephen Warren <swarren@nvidia.com>
13 - if:
17 const: nvidia,tegra210-timer
25 A list of 14 interrupts; one per each timer channels 0 through 13
27 - if:
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Dingenic,tcu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/ingenic,tcu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs Timer/Counter Unit (TCU)
11 Documentation/arch/mips/ingenic-tcu.rst.
14 - Paul Cercueil <paul@crapouillou.net>
21 - ingenic,jz4740-tcu
22 - ingenic,jz4725b-tcu
23 - ingenic,jz4760-tcu
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/Documentation/arch/mips/
Dingenic-tcu.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Ingenic JZ47xx SoCs Timer/Counter Unit hardware
7 The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function
11 - JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all
14 - JZ4725B introduced a separate channel, called Operating System Timer
15 (OST). It is a 32-bit programmable timer. On JZ4760B and above, it is
16 64-bit.
18 - Each one of the TCU channels has its own clock, which can be reparented to three
21 - The watchdog and OST hardware blocks also feature a TCSR register with the same
23 - The TCU registers used to gate/ungate can also gate/ungate the watchdog and
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