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/Documentation/devicetree/bindings/media/xilinx/
Dxlnx,v-tc.txt1 Xilinx Video Timing Controller (VTC)
4 The Video Timing Controller is a general purpose video timing generator and
13 - clocks: Must contain a clock specifier for the VTC core and timing
18 - xlnx,detector: The VTC has a timing detector
19 - xlnx,generator: The VTC has a timing generator
Dxlnx,v-tpg.txt26 - xlnx,vtc: A phandle referencing the Video Timing Controller that generates
29 - timing-gpios: Specifier for a GPIO that controls the timing mux at the TPG
33 The xlnx,vtc and timing-gpios properties are mandatory when the TPG is
44 timing-gpios = <&ps7_gpio_0 55 GPIO_ACTIVE_LOW>;
/Documentation/driver-api/memory-devices/
Dti-gpmc.rst20 GPMC generic timing calculation:
29 generic timing routine was developed to achieve above requirements.
37 happen that timing as specified by peripheral datasheet is not present
38 in timing structure, in this scenario, try to correlate peripheral
39 timing to the one available. If that doesn't work, try to add a new
40 field as required by peripheral, educate generic timing routine to
45 Generic timing routine has been verified to work properly on
48 A word of caution: generic timing routine has been developed based
50 custom timing routines, a kind of reverse engineering without
52 in mainline having custom timing routine) and by simulation.
[all …]
/Documentation/devicetree/bindings/mmc/
Dsdhci-am654.yaml62 description: Output tap delay for SD/MMC legacy timing
68 description: Output tap delay for MMC high speed timing
74 description: Output tap delay for SD high speed timing
80 description: Output tap delay for SD UHS SDR12 timing
86 description: Output tap delay for SD UHS SDR25 timing
92 description: Output tap delay for SD UHS SDR50 timing
98 description: Output tap delay for SD UHS SDR104 timing
104 description: Output tap delay for SD UHS DDR50 timing
110 description: Output tap delay for eMMC DDR52 timing
116 description: Output tap delay for eMMC HS200 timing
[all …]
Dsamsung,exynos-dw-mshc.yaml58 samsung,dw-mshc-ddr-timing:
70 See also samsung,dw-mshc-hs400-timing property.
72 samsung,dw-mshc-hs400-timing:
84 Valid values for SDR and DDR CIU clock timing::
90 If missing, values from samsung,dw-mshc-ddr-timing property are used.
92 samsung,dw-mshc-sdr-timing:
104 See also samsung,dw-mshc-hs400-timing property.
118 - samsung,dw-mshc-ddr-timing
119 - samsung,dw-mshc-sdr-timing
155 samsung,dw-mshc-sdr-timing = <0 4>;
[all …]
Dcdns,sdhci.yaml40 description: Value of the delay in the input path for SD high-speed timing
46 description: Value of the delay in the input path for legacy timing
52 description: Value of the delay in the input path for SD UHS SDR12 timing
58 description: Value of the delay in the input path for SD UHS SDR25 timing
64 description: Value of the delay in the input path for SD UHS SDR50 timing
70 description: Value of the delay in the input path for SD UHS DDR50 timing
76 description: Value of the delay in the input path for MMC high-speed timing
82 description: Value of the delay in the input path for eMMC high-speed DDR timing
/Documentation/devicetree/bindings/mips/cavium/
Dbootbus.txt32 - cavium,t-adr: A cell specifying the ADR timing (in nS).
34 - cavium,t-ce: A cell specifying the CE timing (in nS).
36 - cavium,t-oe: A cell specifying the OE timing (in nS).
38 - cavium,t-we: A cell specifying the WE timing (in nS).
40 - cavium,t-rd-hld: A cell specifying the RD_HLD timing (in nS).
42 - cavium,t-wr-hld: A cell specifying the WR_HLD timing (in nS).
44 - cavium,t-pause: A cell specifying the PAUSE timing (in nS).
46 - cavium,t-wait: A cell specifying the WAIT timing (in nS).
48 - cavium,t-page: A cell specifying the PAGE timing (in nS).
50 - cavium,t-rd-dly: A cell specifying the RD_DLY timing (in nS).
/Documentation/devicetree/bindings/display/panel/
Ddisplay-timings.yaml18 and to specify the timing that is native for the display.
27 The default display timing is the one specified as native-mode.
32 "^timing":
34 $ref: panel-timing.yaml#
42 * Example that specifies panel timing using minimum, typical,
Dpanel-timing.yaml4 $id: http://devicetree.org/schemas/display/panel/panel-timing.yaml#
7 title: panel timing
14 There are different ways of describing the timing data of a panel. The
46 This matches the timing diagrams often found in data sheets.
56 Timing can be specified either as a typical value or as a tuple
73 description: Horizontal front porch panel timing
85 description: Horizontal back porch timing
97 description: Horizontal sync length panel timing
109 description: Vertical front porch panel timing
121 description: Vertical back porch panel timing
[all …]
Dpanel-dpi.yaml28 panel-timing: true
35 - panel-timing
53 panel-timing {
Dsgd,gktw70sdae4se.yaml41 panel-timing: true
52 - panel-timing
64 panel-timing {
Dmitsubishi,aa104xd12.yaml44 panel-timing: true
55 - panel-timing
70 panel-timing {
Dmitsubishi,aa121td01.yaml44 panel-timing: true
55 - panel-timing
69 panel-timing {
Dadvantech,idk-1110wr.yaml41 panel-timing: true
51 - panel-timing
64 panel-timing {
Dinnolux,ee101ia-01d.yaml38 panel-timing: true
46 - panel-timing
Dadvantech,idk-2121wr.yaml40 panel-timing: true
77 - panel-timing
90 panel-timing {
/Documentation/devicetree/bindings/memory-controllers/
Dintel,ixp4xx-expansion-peripheral-props.yaml19 description: Address timing, extend address phase with n cycles.
24 description: Setup chip select timing, extend setup phase with n cycles.
29 description: Strobe timing, extend strobe phase with n cycles.
34 description: Hold timing, extend hold phase with n cycles.
39 description: Recovery timing, extend recovery phase with n cycles.
/Documentation/w1/masters/
Dw1-uart.rst14 Serial Device Bus to create the 1-Wire timing patterns as described in
20 open-drain mode. The timing patterns are generated by a specific
24 For instance the timing pattern for a 1-Wire reset and presence detect uses
39 to generate the 1-Wire timing patterns.
/Documentation/devicetree/bindings/ata/
Dceva,ahci-1v84.yaml44 OOB timing value for COMINIT parameter for port 0.
56 OOB timing value for COMWAKE parameter for port 0.
68 Burst timing value for COM parameter for port 0.
80 Retry interval timing value for port 0.
90 OOB timing value for COMINIT parameter for port 1.
102 OOB timing value for COMWAKE parameter for port 1.
114 Burst timing value for COM parameter for port 1.
126 Retry interval timing value for port 1.
/Documentation/devicetree/bindings/w1/
Dw1-uart.yaml14 to create the 1-Wire timing patterns.
17 mode. The timing patterns are generated by a specific combination of
24 to generate the 1-Wire timing patterns.
/Documentation/userspace-api/media/v4l/
Dvidioc-g-dv-timings.rst48 applications use the :ref:`VIDIOC_G_DV_TIMINGS <VIDIOC_G_DV_TIMINGS>` ioctl. The detailed timing
52 structure as argument. If the ioctl is not supported or the timing
187 - Type of DV timings as listed in :ref:`dv-timing-types`.
201 .. _dv-timing-types:
203 .. flat-table:: DV Timing types
208 * - Timing type
224 .. flat-table:: DV BT Timing standards
228 * - Timing standard
249 .. flat-table:: DV BT Timing flags
/Documentation/gpu/amdgpu/display/
Ddc-glossary.rst77 Vertical Timing Generator
198 Output Pipe Timing Combiner
201 Output Timing Generator
/Documentation/devicetree/bindings/memory-controllers/fsl/
Dfsl,imx-weim.yaml96 - fsl,weim-cs-timing
135 fsl,weim-cs-timing:
151 fsl,weim-cs-timing:
170 fsl,weim-cs-timing:
198 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
Dfsl,imx-weim-peripherals.yaml23 fsl,weim-cs-timing:
26 Timing values for the child node.
/Documentation/devicetree/bindings/media/i2c/
Ddongwoon,dw9768.yaml49 dongwoon,aac-timing:
51 Number of AAC Timing count that controlled by one 6-bit period of
93 dongwoon,aac-timing = <0x39>;

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