| /Documentation/networking/device_drivers/ethernet/mellanox/mlx5/ |
| D | tracepoints.rst | 11 kernel tracepoints interfaces (refer to Documentation/trace/ftrace.rst).
17 - mlx5e_configure_flower: trace flower filter actions and cookies offloaded to mlx5::
20 $ cat /sys/kernel/tracing/trace
24 - mlx5e_delete_flower: trace flower filter actions and cookies deleted from mlx5::
27 $ cat /sys/kernel/tracing/trace
31 - mlx5e_stats_flower: trace flower stats request::
34 $ cat /sys/kernel/tracing/trace
38 - mlx5e_tc_update_neigh_used_value: trace tunnel rule neigh update value offloaded to mlx5::
41 $ cat /sys/kernel/tracing/trace
45 - mlx5e_rep_neigh_update: trace neigh update tasks scheduled due to neigh state change events::
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| /Documentation/trace/ |
| D | intel_th.rst | 4 Intel(R) Trace Hub (TH)
10 Intel(R) Trace Hub (TH) is a set of hardware blocks that produce,
11 switch and output trace data from multiple hardware and software
12 sources over several types of trace output ports encoded in System
13 Trace Protocol (MIPI STPv2) and is intended to perform full system
14 debugging. For more information on the hardware, see Intel(R) Trace
17 It consists of trace sources, trace destinations (outputs) and a
18 switch (Global Trace Hub, GTH). These devices are placed on a bus of
23 - Software Trace Hub (STH), trace source, which is a System Trace
25 - Memory Storage Unit (MSU), trace output, which allows storing
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| D | stm.rst | 4 System Trace Module
7 System Trace Module (STM) is a device described in MIPI STP specs as
8 STP trace stream generator. STP (System Trace Protocol) is a trace
9 protocol multiplexing data from multiple trace sources, each one of
12 hardware trace sources, others are available to software. Software
13 trace sources are usually free to pick for themselves any
16 On the receiving end of this STP stream (the decoder side), trace
18 order for the decoder to be able to make sense of the trace that
19 involves multiple trace sources, it needs to be able to map those
20 master/channel pairs to the trace sources that it understands.
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| D | events-msr.rst | 2 MSR Trace Events
9 Available trace points:
13 Trace MSR reads:
22 Trace MSR writes:
31 Trace RDPMC in kernel:
35 The trace data can be post processed with the postprocess/decode_msr.py script::
37 cat /sys/kernel/tracing/trace | decode_msr.py /usr/src/linux/include/asm/msr-index.h
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| D | hisi-ptt.rst | 4 HiSilicon PCIe Tune and Trace device
10 HiSilicon PCIe tune and trace device (PTT) is a PCIe Root Complex
13 and trace the TLP headers (trace). The two functions are independent,
110 Trace chapter
113 PTT trace is designed for dumping the TLP headers to the memory, which
117 device. It's also supported to trace the headers of certain type and of
121 trace and get the data. It's also supported to decode the trace
122 data with `perf report`. The control parameters for trace is inputted
130 This will trace the TLP headers downstream root port 0000:00:10.1 (event
137 The TLP headers to trace can be filtered by the Root Ports or the Requester ID
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| D | debugging.rst | 29 in normal, softirq, interrupt and even NMI context. The trace data is
35 the trace is being recorded.
38 a subsystem of the kernel. If you need debugging traces, add trace events
98 location 0x284500000. Then the trace_instance option will create a trace
109 reserve_mem=12M:4096:trace trace_instance=boot_map@trace
112 boot up, and align it by 4096 bytes. It will label this memory as "trace"
116 memory reserved by reserve_mem that was labeled as "trace". This method is
126 reserve_mem=12M:0x2000000:trace trace_instance=boot_map@trace
154 reserve_mem=12M:4096:trace trace_instance=boot_map^traceprintk^traceoff@trace
158 Otherwise the trace from the most recent boot will be mixed with the trace
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| D | events.rst | 11 Tracepoints (see Documentation/trace/tracepoints.rst) can be used
105 Each trace event has a 'format' file associated with it that contains
107 be used to parse the binary trace stream, and is also the place to
123 where offset is the offset of the field in the trace record and size
156 Trace events can be filtered in the kernel by associating boolean
158 the trace buffer, its fields are checked against the filter expression
160 'match' the filter will appear in the trace output, and an event whose
181 'format' files for trace events (see section 4).
298 effect) trace output. Only filters that reference just the common
346 Will only trace events for the current task.
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| D | ftrace.rst | 43 See Documentation/trace/ftrace-design.rst for details for arch porters and such.
110 This sets or displays whether writing to the trace
125 trace:
127 This file holds the output of the trace in a human
138 The output is the same as the "trace" file but this
141 retrieved. Unlike the "trace" file, this file is a
146 "trace" file is static, and if the tracer is not
160 trace option (also in trace_options). Options may also be set
168 The maximum time is saved in this file. The max trace will also be
169 stored, and displayed by "trace". A new max trace will only be
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| /Documentation/trace/coresight/ |
| D | coresight-etm4x-reference.rst | 23 :Trace Registers: {CONFIGR + others}
25 Bit select trace features. See ‘mode’ section below. Bits
26 in this will cause equivalent programming of trace config and
32 bitfield up to 32 bits setting trace features.
40 :Trace Registers: All
42 Reset all programming to trace nothing / no logic programmed.
50 :Trace Registers: PRGCTLR, All hardware regs.
53 and enables trace.
55 - = 0 : disable trace hardware.
63 :Trace Registers: None.
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| /Documentation/devicetree/bindings/arm/ |
| D | arm,embedded-trace-extension.yaml | 5 $id: http://devicetree.org/schemas/arm/arm,embedded-trace-extension.yaml#
8 title: ARM Embedded Trace Extensions
15 Arm Embedded Trace Extension(ETE) is a per CPU trace component that
18 The trace generated by the ETE could be stored via legacy CoreSight
20 Arm Trace Buffer Extension (TRBE)). Since the ETE can be connected to
29 - const: arm,embedded-trace-extension
41 Output connections from the ETE to legacy CoreSight trace bus.
45 description: Output connection from the ETE to legacy CoreSight Trace bus.
59 compatible = "arm,embedded-trace-extension";
65 compatible = "arm,embedded-trace-extension";
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| D | arm,coresight-tpiu.yaml | 7 title: Arm CoreSight Trace Port Interface Unit
18 SoCs tracing needs. These trace components can generally be classified as
19 sinks, links and sources. Trace data produced by one or more sources flows
23 The CoreSight Trace Port Interface Unit captures trace data from the trace bus
24 and outputs it to an external trace port.
66 description: Input connection from the CoreSight Trace bus.
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| D | arm,trace-buffer-extension.yaml | 5 $id: http://devicetree.org/schemas/arm/arm,trace-buffer-extension.yaml#
8 title: ARM Trace Buffer Extensions
14 Arm Trace Buffer Extension (TRBE) is a per CPU component
15 for storing trace generated on the CPU to memory. It is
26 - const: arm,trace-buffer-extension
47 compatible = "arm,trace-buffer-extension";
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| D | arm,coresight-static-replicator.yaml | 7 title: Arm CoreSight Static Trace Bus Replicator
18 SoCs tracing needs. These trace components can generally be classified as
19 sinks, links and sources. Trace data produced by one or more sources flows
23 The Coresight replicator splits a single trace stream into two trace streams
24 for systems that have more than one trace sink component.
39 description: Input connection from CoreSight Trace bus
47 description: Output connections to CoreSight Trace bus
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| D | arm,coresight-tmc.yaml | 7 title: Arm CoreSight Trace Memory Controller
18 SoCs tracing needs. These trace components can generally be classified as
19 sinks, links and sources. Trace data produced by one or more sources flows
23 Trace Memory Controller is used for Embedded Trace Buffer(ETB), Embedded Trace
24 FIFO(ETF) and Embedded Trace Router(ETR) configurations. The configuration
68 Size of contiguous buffer space for TMC ETR (embedded trace router). The
91 description: Input connection from the CoreSight Trace bus.
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| D | arm,coresight-static-funnel.yaml | 7 title: Arm CoreSight Static Trace Bus Funnel
18 SoCs tracing needs. These trace components can generally be classified as
19 sinks, links and sources. Trace data produced by one or more sources flows
23 The Coresight static funnel merges 2-8 trace sources into a single trace
38 description: Input connections from CoreSight Trace bus
47 description: Output connection to CoreSight Trace bus
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| D | arm,coresight-dynamic-replicator.yaml | 7 title: Arm Coresight Programmable Trace Bus Replicator
18 SoCs tracing needs. These trace components can generally be classified as
19 sinks, links and sources. Trace data produced by one or more sources flows
23 The Coresight replicator splits a single trace stream into two trace streams
24 for systems that have more than one trace sink component.
72 description: Input connection from CoreSight Trace bus
80 description: Output connections to CoreSight Trace bus
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| D | arm,coresight-etm.yaml | 7 title: Arm CoreSight Embedded Trace MacroCell
18 SoCs tracing needs. These trace components can generally be classified as
19 sinks, links and sources. Trace data produced by one or more sources flows
23 The Embedded Trace Macrocell (ETM) is a real-time trace module providing
53 Embedded Trace Macrocell with memory mapped access.
60 Embedded Trace Macrocell (version 4.x), with system register access only
97 Indicates that an implementation can skip powering up the trace unit.
114 description: Output connection from the ETM to CoreSight Trace bus.
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| D | arm,coresight-dynamic-funnel.yaml | 7 title: Arm CoreSight Programmable Trace Bus Funnel
18 SoCs tracing needs. These trace components can generally be classified as
19 sinks, links and sources. Trace data produced by one or more sources flows
23 The Coresight funnel merges 2-8 trace sources into a single trace
65 description: Input connections from CoreSight Trace bus
74 description: Output connection to CoreSight Trace bus
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| D | arm,coresight-stm.yaml | 7 title: Arm CoreSight System Trace MacroCell
18 SoCs tracing needs. These trace components can generally be classified as
19 sinks, links and sources. Trace data produced by one or more sources flows
23 The STM is a trace source that is integrated into a CoreSight system, designed
24 primarily for high-bandwidth trace of instrumentation embedded into software.
73 description: Output connection to the CoreSight Trace bus.
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| D | qcom,coresight-remote-etm.yaml | 7 title: Qualcomm Coresight Remote ETM(Embedded Trace Macrocell)
14 Support for ETM trace collection on remote processor using coresight
16 processor like modem processor via sysfs and collecting the trace
29 description: Output connection to the CoreSight Trace bus.
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| /Documentation/tools/rtla/ |
| D | common_osnoise_options.rst | 3 Set the automatic trace mode. This mode sets some commonly used options
16 Stop the trace if a single sample is higher than the argument in microseconds.
17 If **-T** is set, it will also save the trace to the output.
21 Stop the trace if the total sample is higher than the argument in microseconds.
22 If **-T** is set, it will also save the trace to the output.
29 **-t**, **--trace** \[*file*]
31 Save the stopped trace to [*file|osnoise_trace.txt*].
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| D | common_timerlat_options.rst | 3 Set the automatic trace mode. This mode sets some commonly used options
14 Stop trace if the *IRQ* latency is higher than the argument in us.
18 Stop trace if the *Thread* latency is higher than the argument in us.
22 Save the stack trace at the *IRQ* if a *Thread* latency is higher than the
25 **-t**, **--trace** \[*file*]
27 Save the stopped trace to [*file|timerlat_trace.txt*].
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| /Documentation/arch/powerpc/ |
| D | imc.rst | 92 IMC Trace-mode
95 POWER9 supports two modes for IMC which are the Accumulation mode and Trace
98 Trace mode, the 64 bit trace SCOM value is initialized with the event
99 information. The CPMCxSEL and CPMC_LOAD in the trace SCOM, specifies the event
105 whether hardware is configured for accumulation or trace mode.
115 | | 1: Trace Mode |
152 *Currently the event monitored for trace-mode is fixed as cycle.*
154 Trace IMC example usage
163 To record an application/process with trace-imc event:
173 Benefits of using IMC trace-mode
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| /Documentation/core-api/ |
| D | tracepoint.rst | 31 ``Documentation/trace/*`` directory.
36 .. kernel-doc:: include/trace/events/irq.h
42 .. kernel-doc:: include/trace/events/signal.h
48 .. kernel-doc:: include/trace/events/block.h
54 .. kernel-doc:: include/trace/events/workqueue.h
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-event_source-devices-hisi_ptt | 9 See Documentation/trace/hisi-ptt.rst for more information.
68 information used for PTT trace. Each file is named after the supported
71 See the description of the "filter" in Documentation/trace/hisi-ptt.rst
87 can be used to control the TLP headers to trace by the PTT trace.
94 information used for PTT trace. Each file is named after the supported
97 See the description of the "filter" in Documentation/trace/hisi-ptt.rst
113 can be used to control the TLP headers to trace by the PTT trace.
|