| /Documentation/devicetree/bindings/serial/ |
| D | mediatek,uart.yaml | 4 $id: http://devicetree.org/schemas/serial/mediatek,uart.yaml#
7 title: MediaTek Universal Asynchronous Receiver/Transmitter (UART)
16 The MediaTek UART is based on the basic 8250 UART and compatible
23 - const: mediatek,mt6577-uart
26 - mediatek,mt2701-uart
27 - mediatek,mt2712-uart
28 - mediatek,mt6580-uart
29 - mediatek,mt6582-uart
30 - mediatek,mt6589-uart
31 - mediatek,mt6755-uart
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| D | mvebu-uart.txt | 1 * Marvell UART : Non standard UART used in some of Marvell EBU SoCs
6 - "marvell,armada-3700-uart" for the standard variant of the UART
9 - "marvell,armada-3700-uart-ext" for the extended variant of the
10 UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit
13 - clocks: UART reference clock used to derive the baudrate. If no clock
14 is provided (possible only with the "marvell,armada-3700-uart"
18 for standard variant of UART and UART2-clk for extended variant
19 of UART. TBG clock (with UART TBG divisors d1=d2=1) or xtal clock
23 (marvell,armada-3700-uart): "uart-sum", "uart-tx" and "uart-rx",
24 respectively the UART sum interrupt, the UART TX interrupt and
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| D | amlogic,meson-uart.yaml | 5 $id: http://devicetree.org/schemas/serial/amlogic,meson-uart.yaml#
8 title: Amlogic Meson SoC UART Serial Interface
14 The Amlogic Meson SoC UART Serial Interface is present on a large range
28 - description: Always-on power domain UART controller
31 - amlogic,meson6-uart
32 - amlogic,meson8-uart
33 - amlogic,meson8b-uart
34 - amlogic,meson-gx-uart
35 - amlogic,meson-s4-uart
36 - amlogic,meson-a1-uart
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| D | samsung_uart.yaml | 7 title: Samsung S3C, S5P, Exynos, and S5L (Apple SoC) SoC UART Controller
14 Each Samsung UART should have an alias correctly numbered in the "aliases"
22 - apple,s5l-uart
23 - axis,artpec8-uart
24 - google,gs101-uart
25 - samsung,s3c6400-uart
26 - samsung,s5pv210-uart
27 - samsung,exynos4210-uart
28 - samsung,exynos5433-uart
29 - samsung,exynos850-uart
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| D | fsl-imx-uart.yaml | 4 $id: http://devicetree.org/schemas/serial/fsl-imx-uart.yaml#
7 title: Freescale i.MX Universal Asynchronous Receiver/Transmitter (UART)
15 - const: fsl,imx1-uart
16 - const: fsl,imx21-uart
19 - fsl,imx25-uart
20 - fsl,imx27-uart
21 - fsl,imx31-uart
22 - fsl,imx35-uart
23 - fsl,imx50-uart
24 - fsl,imx51-uart
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| D | snps-dw-apb-uart.yaml | 4 $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
7 title: Synopsys DesignWare ABP UART
20 const: starfive,jh7110-uart
35 - renesas,r9a06g032-uart
36 - renesas,r9a06g033-uart
37 - const: renesas,rzn1-uart
40 - rockchip,px30-uart
41 - rockchip,rk1808-uart
42 - rockchip,rk3036-uart
43 - rockchip,rk3066-uart
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| D | sprd-uart.yaml | 5 $id: http://devicetree.org/schemas/serial/sprd-uart.yaml#
8 title: Spreadtrum serial UART
20 - sprd,sc9860-uart
21 - sprd,sc9863a-uart
22 - sprd,ums512-uart
23 - sprd,ums9620-uart
24 - const: sprd,sc9836-uart
25 - const: sprd,sc9836-uart
39 "enable" for UART module enable clock, "uart" for UART clock, "source"
40 for UART source (parent) clock.
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| D | brcm,bcm7271-uart.yaml | 4 $id: http://devicetree.org/schemas/serial/brcm,bcm7271-uart.yaml#
16 The Broadcom UART is based on the basic 8250 UART but with
24 - brcm,bcm7271-uart
25 - brcm,bcm7278-uart
32 description: The UART register block and optionally the DMA register blocks.
35 - const: uart
37 - const: uart
54 description: The UART interrupt and optionally the DMA interrupt.
57 - const: uart
74 compatible = "brcm,bcm7271-uart";
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| D | 8250.yaml | 7 title: UART (Universal Asynchronous Receiver/Transmitter)
30 const: mrvl,mmp-uart
62 - const: intel,xscale-uart
63 - const: mrvl,pxa-uart
64 - const: nuvoton,wpcm450-uart
65 - const: nuvoton,npcm750-uart
66 - const: nvidia,tegra20-uart
67 - const: nxp,lpc3220-uart
82 - nxp,lpc1850-uart
84 - ti,da830-uart
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| D | ingenic,uart.yaml | 4 $id: http://devicetree.org/schemas/serial/ingenic,uart.yaml#
7 title: Ingenic SoCs UART controller
22 - ingenic,jz4740-uart
23 - ingenic,jz4750-uart
24 - ingenic,jz4760-uart
25 - ingenic,jz4780-uart
26 - ingenic,x1000-uart
29 - ingenic,jz4770-uart
30 - ingenic,jz4775-uart
31 - const: ingenic,jz4760-uart
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| D | 8250_omap.yaml | 20 - ti,am3352-uart
21 - ti,am4372-uart
22 - ti,am654-uart
23 - ti,dra742-uart
24 - ti,omap2-uart
25 - ti,omap3-uart
26 - ti,omap4-uart
29 - ti,am64-uart
30 - ti,j721e-uart
31 - const: ti,am654-uart
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| D | cirrus,clps711x-uart.txt | 1 * Cirrus Logic CLPS711X Universal Asynchronous Receiver/Transmitter (UART)
4 - compatible: Should be "cirrus,ep7209-uart".
6 - interrupts: Should contain UART TX and RX interrupt.
7 - clocks: Should contain UART core clock number.
8 - syscon: Phandle to SYSCON node, which contain UART control bits.
14 Note: Each UART port should have an alias correctly numbered
22 uart1: uart@80000480 {
23 compatible = "cirrus,ep7312-uart","cirrus,ep7209-uart";
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| D | sifive-serial.yaml | 7 title: SiFive asynchronous serial interface (UART)
21 - sifive,fu540-c000-uart
22 - sifive,fu740-c000-uart
27 Should be something similar to "sifive,<chip>-uart"
28 for the UART as integrated on a particular chip,
29 and "sifive,uart<version>" for the general UART IP
32 UART HDL that corresponds to the IP block version
35 https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/uart
58 compatible = "sifive,fu540-c000-uart", "sifive,uart0";
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| D | renesas,em-uart.yaml | 4 $id: http://devicetree.org/schemas/serial/renesas,em-uart.yaml#
7 title: Renesas EMMA Mobile UART Interface
17 - renesas,r9a09g011-uart # RZ/V2M
18 - const: renesas,em-uart # generic EMMA Mobile compatible UART
21 - const: renesas,em-uart # generic EMMA Mobile compatible UART
32 - description: UART functional clock
55 const: renesas,r9a09g011-uart
69 compatible = "renesas,em-uart";
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| D | cdns,uart.yaml | 4 $id: http://devicetree.org/schemas/serial/cdns,uart.yaml#
7 title: Cadence UART Controller
15 - description: UART controller for Zynq-7xxx SoC
18 - const: cdns,uart-r1p8
19 - description: UART controller for Zynq Ultrascale+ MPSoC
21 - const: xlnx,zynqmp-uart
22 - const: cdns,uart-r1p12
66 const: cdns,uart-r1p8
76 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
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| D | esp,esp32-uart.yaml | 5 $id: http://devicetree.org/schemas/serial/esp,esp32-uart.yaml#
8 title: ESP32xx UART controllers
14 ESP32 UART controller is a part of the ESP32 SoC.
15 ESP32S3 UART controller is a part of the ESP32S3 SoC.
24 - esp,esp32-uart
25 - esp,esp32s3-uart
47 compatible = "esp,esp32s3-uart";
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| D | arc-uart.txt | 1 * Synopsys ARC UART : Non standard UART used in some of the ARC FPGA boards
4 - compatible : "snps,arc-uart"
7 - clock-frequency : the input clock frequency for the UART
8 - current-speed : baud rate for UART
13 compatible = "snps,arc-uart";
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| D | serial.yaml | 18 Each enabled UART may have an optional "serialN" alias in the "aliases" node,
32 the UART's CTS line.
38 the UART's DCD line.
44 the UART's DSR line.
50 the UART's DTR line.
56 the UART's RNG line.
62 the UART's RTS line.
64 uart-has-rtscts:
67 The presence of this property indicates that the UART has dedicated lines
70 UART hardware and the board wiring.
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| D | actions,owl-uart.yaml | 4 $id: http://devicetree.org/schemas/serial/actions,owl-uart.yaml#
7 title: Actions Semi Owl UART
19 - actions,s500-uart
20 - actions,s900-uart
21 - const: actions,owl-uart
44 compatible = "actions,s500-uart", "actions,owl-uart";
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| D | st,stm32-uart.yaml | 4 $id: http://devicetree.org/schemas/serial/st,stm32-uart.yaml#
15 - st,stm32-uart
16 - st,stm32f7-uart
17 - st,stm32h7-uart
32 description: label associated with this uart
50 # cts-gpios and rts-gpios properties can be used instead of 'uart-has-rtscts'
54 # It should be noted that both cts-gpios/rts-gpios and 'uart-has-rtscts' or
93 const: st,stm32-uart
102 - st,stm32-uart
103 - st,stm32f7-uart
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| /Documentation/devicetree/bindings/dma/ |
| D | mediatek,uart-dma.yaml | 4 $id: http://devicetree.org/schemas/dma/mediatek,uart-dma.yaml#
7 title: MediaTek UART APDMA controller
13 The MediaTek UART APDMA controller provides DMA capabilities
14 for the UART peripheral bus.
24 - mediatek,mt2712-uart-dma
25 - mediatek,mt6795-uart-dma
26 - mediatek,mt8365-uart-dma
27 - mediatek,mt8516-uart-dma
28 - const: mediatek,mt6577-uart-dma
30 - mediatek,mt6577-uart-dma
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| /Documentation/devicetree/bindings/soc/aspeed/ |
| D | uart-routing.yaml | 6 $id: http://devicetree.org/schemas/soc/aspeed/uart-routing.yaml#
9 title: Aspeed UART Routing Controller
16 The Aspeed UART routing control allow to dynamically route the inputs for
19 This allows, for example, to connect the output of UART to another UART.
31 - aspeed,ast2400-uart-routing
32 - aspeed,ast2500-uart-routing
33 - aspeed,ast2600-uart-routing
52 uart_routing: uart-routing@98 {
53 compatible = "aspeed,ast2600-uart-routing";
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| /Documentation/devicetree/bindings/clock/ |
| D | marvell,armada-3700-uart-clock.yaml | 4 $id: http://devicetree.org/schemas/clock/marvell,armada-3700-uart-clock.yaml#
6 title: Marvell Armada 3720 UART clocks
13 const: marvell,armada-3700-uart-clock
17 - description: UART Clock Control Register
18 - description: UART 2 Baud Rate Divisor Register
22 List of parent clocks suitable for UART from following set:
24 UART clock can use one from this set and when more are provided
28 used for UART (most probably xtal) for smooth boot log on UART.
54 compatible = "marvell,armada-3700-uart-clock";
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| /Documentation/devicetree/bindings/soc/fsl/cpm_qe/ |
| D | serial.txt | 4 - fsl,cpm1-smc-uart
5 - fsl,cpm2-smc-uart
6 - fsl,cpm1-scc-uart
7 - fsl,cpm2-scc-uart
8 - fsl,qe-uart
23 compatible = "fsl,mpc8272-scc-uart",
24 "fsl,cpm2-scc-uart";
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| /Documentation/w1/masters/ |
| D | w1-uart.rst | 4 Kernel driver w1-uart
13 UART 1-Wire bus driver. The driver utilizes the UART interface via the
15 the document `"Using a UART to Implement a 1-Wire Bus Master"`_.
17 .. _"Using a UART to Implement a 1-Wire Bus Master": https://www.analog.com/en/technical-articles/u…
19 In short, the UART peripheral must support full-duplex and operate in
26 UART (least significant bit first, start-bit low) sets the reset low time
45 Specify the UART 1-wire bus in the device tree by adding the single child
52 compatible = "w1-uart";
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