Searched full:uarts (Results 1 – 18 of 18) sorted by relevance
| /Documentation/devicetree/bindings/soc/aspeed/ |
| D | uart-routing.yaml | 17 the built-in UARTS and physical serial I/O ports.
20 This can be used to enable Host <-> BMC communication via UARTs, e.g. to
24 which owns the system configuration policy, to configure how UARTs and
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| /Documentation/translations/zh_CN/arch/loongarch/ |
| D | irq-chip-model.rst | 27 CPU串口（UARTs）中断发送到LIOINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/
36 | LIOINTC | <-- | UARTs |
63 CPU串口（UARTs）中断发送到LIOINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/
72 | EIOINTC | | LIOINTC | <-- | UARTs |
94 CPU串口（UARTs）中断发送到LIOINTC，PCH-MSI中断发送到AVECINTC，而后通过AVECINTC直接
104 | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs |
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| /Documentation/translations/zh_TW/arch/loongarch/ |
| D | irq-chip-model.rst | 27 CPU串口（UARTs）中斷髮送到LIOINTC，而其他所有設備的中斷則分別發送到所連接的PCH-PIC/
36 | LIOINTC | <-- | UARTs |
63 CPU串口（UARTs）中斷髮送到LIOINTC，而其他所有設備的中斷則分別發送到所連接的PCH-PIC/
72 | EIOINTC | | LIOINTC | <-- | UARTs |
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| /Documentation/arch/loongarch/ |
| D | irq-chip-model.rst | 23 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
33 | LIOINTC | <-- | UARTs |
60 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
70 | EIOINTC | | LIOINTC | <-- | UARTs |
92 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, PCH-MSI interrupts go
102 | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs |
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | brcm,bcm7120-l2-intc.yaml | 24 controller, in particular for UARTs
116 typically UARTs. Setting these bits will make their respective interrupt
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| /Documentation/devicetree/bindings/serial/ |
| D | 8250_omap.yaml | 7 title: 8250 compliant UARTs on TI's OMAP2+ and K3 SoCs
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| D | qcom,msm-uartdm.yaml | 20 Note:: Aliases may be defined to ensure the correct ordering of the UARTs.
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| D | serial.yaml | 14 This document lists a set of generic properties for describing UARTs in a
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | starfive,jh7110-sys-pinctrl.yaml | 16 includes a number of other UARTs, I2Cs, SPIs, PWMs etc.
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| D | starfive,jh7100-pinctrl.yaml | 41 UARTs, I2Cs, SPIs, PWMs etc. All these peripherals are connected to all 64
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| /Documentation/driver-api/serial/ |
| D | serial-iso7816.rst | 14 Some CPUs/UARTs (e.g., Microchip AT91) contain a built-in mode capable of
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| D | serial-rs485.rst | 18 Some CPUs/UARTs (e.g., Atmel AT91 or 16C950 UART) contain a built-in
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| /Documentation/devicetree/bindings/bus/ |
| D | nvidia,tegra20-gmi.txt | 5 synchronous/asynchronous NOR, FPGA, UARTS and more.
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| /Documentation/devicetree/bindings/mfd/ |
| D | aspeed-lpc.yaml | 100 The UARTs present in the ASPEED SoC can have their resets tied to the reset
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| /Documentation/firmware-guide/acpi/ |
| D | enumeration.rst | 23 that standard UARTs are not busses so there is no struct uart_device,
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| /Documentation/arch/arm64/ |
| D | arm-acpi.rst | 422 to the kernel. This has implications for devices such as UARTs, or SoC-driven
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| /Documentation/dev-tools/ |
| D | kgdb.rst | 835 kgdboc and uarts
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| /Documentation/admin-guide/ |
| D | kernel-parameters.txt | 4220 nr_uarts= [SERIAL] maximum number of UARTs to be registered.
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