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/Documentation/devicetree/bindings/phy/
Dqcom,sc8280xp-qmp-ufs-phy.yaml4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-ufs-phy.yaml#
7 title: Qualcomm QMP PHY controller (UFS, SC8280XP)
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
19 - qcom,msm8996-qmp-ufs-phy
20 - qcom,msm8998-qmp-ufs-phy
21 - qcom,sa8775p-qmp-ufs-phy
22 - qcom,sc7180-qmp-ufs-phy
23 - qcom,sc7280-qmp-ufs-phy
24 - qcom,sc8180x-qmp-ufs-phy
25 - qcom,sc8280xp-qmp-ufs-phy
[all …]
Dmediatek,ufs-phy.yaml5 $id: http://devicetree.org/schemas/phy/mediatek,ufs-phy.yaml#
8 title: MediaTek Universal Flash Storage (UFS) M-PHY
15 UFS M-PHY nodes are defined to describe on-chip UFS M-PHY hardware macro.
16 Each UFS M-PHY node should have its own node.
17 To bind UFS M-PHY with UFS host controller, the controller node should
18 contain a phandle reference to UFS M-PHY node.
22 pattern: "^ufs-phy@[0-9a-f]+$"
60 ufsphy: ufs-phy@11fa0000 {
Dsamsung,ufs-phy.yaml4 $id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
7 title: Samsung SoC series UFS PHY
18 - google,gs101-ufs-phy
19 - samsung,exynos7-ufs-phy
20 - samsung,exynosautov9-ufs-phy
21 - tesla,fsd-ufs-phy
45 control pmu registers bits for ufs m-phy
65 const: samsung,exynos7-ufs-phy
99 ufs_phy: ufs-phy@15571800 {
100 compatible = "samsung,exynos7-ufs-phy";
/Documentation/scsi/
Dufs.rst11 2. UFS Architecture Overview
13 2.2 UFS Transport Protocol (UTP) layer
14 2.3 UFS Interconnect (UIC) Layer
16 3.1 UFS controller initialization
18 3.3 UFS error handling
21 5. UFS Reference Clock Frequency configuration
27 Universal Flash Storage (UFS) is a storage specification for flash devices.
31 is defined by JEDEC Solid State Technology Association. UFS is based
32 on the MIPI M-PHY physical layer standard. UFS uses MIPI M-PHY as the
35 The main goals of UFS are to provide:
[all …]
/Documentation/devicetree/bindings/ufs/
Dsamsung,exynos-ufs.yaml4 $id: http://devicetree.org/schemas/ufs/samsung,exynos-ufs.yaml#
7 title: Samsung SoC series UFS host controller
13 Each Samsung UFS host controller instance should have its own node.
18 - google,gs101-ufs
19 - samsung,exynos7-ufs
20 - samsung,exynosautov9-ufs
21 - samsung,exynosautov9-ufs-vh
22 - tesla,fsd-ufs
29 - description: UFS protector register
41 - description: ufs link core clock
[all …]
Dhisilicon,ufs.yaml4 $id: http://devicetree.org/schemas/ufs/hisilicon,ufs.yaml#
7 title: HiSilicon Universal Flash Storage (UFS) Controller
12 # Select only our matches, not all jedec,ufs
18 - hisilicon,hi3660-ufs
19 - hisilicon,hi3670-ufs
24 - $ref: ufs-common.yaml
30 - const: hisilicon,hi3660-ufs
31 - const: jedec,ufs-1.1
34 - hisilicon,hi3670-ufs
35 - const: jedec,ufs-2.1
[all …]
Dsprd,ums9620-ufs.yaml4 $id: http://devicetree.org/schemas/ufs/sprd,ums9620-ufs.yaml#
7 title: Unisoc Universal Flash Storage (UFS) Controller
13 - $ref: ufs-common.yaml
17 const: sprd,ums9620-ufs
43 sprd,ufs-anlg-syscon:
45 description: phandle of syscon used to control ufs analog regs.
65 ufs: ufs@22000000 {
66 compatible = "sprd,ums9620-ufs";
77 sprd,ufs-anlg-syscon = <&anlg_phy_g12_regs>;
Dmediatek,ufs.yaml4 $id: http://devicetree.org/schemas/ufs/mediatek,ufs.yaml#
7 title: Mediatek Universal Flash Storage (UFS) Controller
13 - $ref: ufs-common.yaml
26 - const: ufs
36 mediatek,ufs-disable-mcq:
38 description: The mask to disable MCQ (Multi-Circular Queue) for UFS host.
59 ufs@ff3c0000 {
66 clock-names = "ufs";
Dti,j721e-ufs.yaml4 $id: http://devicetree.org/schemas/ufs/ti,j721e-ufs.yaml#
7 title: TI J721e UFS Host Controller Glue Driver
15 - const: ti,j721e-ufs
19 description: address of TI UFS glue registers
49 "^ufs@[0-9a-f]+$":
52 Cadence UFS controller node must be the child node.
66 ufs-wrapper@4e80000 {
67 compatible = "ti,j721e-ufs";
78 ufs@4000 {
79 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
Drenesas,ufs.yaml4 $id: http://devicetree.org/schemas/ufs/renesas,ufs.yaml#
7 title: Renesas R-Car UFS Host Controller
13 - $ref: ufs-common.yaml
17 const: renesas,r8a779f0-ufs
52 ufs: ufs@e686000 {
53 compatible = "renesas,r8a779f0-ufs";
Dcdns,ufshc.yaml4 $id: http://devicetree.org/schemas/ufs/cdns,ufshc.yaml#
7 title: Cadence Universal Flash Storage (UFS) Controller
12 # Select only our matches, not all jedec,ufs-2.0
24 - $ref: ufs-common.yaml
31 # CDNS UFS HC + M31 16nm PHY
33 - const: jedec,ufs-2.0
66 ufs@fd030000 {
67 compatible = "cdns,ufshc", "jedec,ufs-2.0";
Dsnps,tc-dwc-g210.yaml4 $id: http://devicetree.org/schemas/ufs/snps,tc-dwc-g210.yaml#
7 title: Synopsys DesignWare Universal Flash Storage (UFS) Controller
12 # Select only our matches, not all jedec,ufs
23 - $ref: ufs-common.yaml
32 - const: jedec,ufs-2.0
45 ufs@d0000000 {
48 "jedec,ufs-2.0";
Dqcom,ufs.yaml4 $id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#
7 title: Qualcomm Universal Flash Storage (UFS) Controller
13 # Select only our matches, not all jedec,ufs-2.0
45 - const: jedec,ufs-2.0
63 - const: ufs-ddr
64 - const: cpu-ufs
109 GPIO connected to the RESET pin of the UFS memory device.
116 - $ref: ufs-common.yaml
304 ufs@1d84000 {
306 "jedec,ufs-2.0";
[all …]
Dufs-common.yaml4 $id: http://devicetree.org/schemas/ufs/ufs-common.yaml#
7 title: Common properties for Universal Flash Storage (UFS) Host Controllers
56 Phandle to UFS host controller supply regulator node.
73 For embedded UFS devices, valid VCC range is 1.7-1.95V or 2.7-3.6V. This
75 1.7-1.95V. Note for external UFS cards this property is invalid and valid
/Documentation/ABI/testing/
Dsysfs-driver-ufs6 UFS host controller. A value of '0' means auto-hibernate is not
8 idle time before the UFS host controller will autonomously put
12 maximum value of 102300000. Refer to the UFS Host Controller
16 What: /sys/bus/platform/devices/*.ufs/device_descriptor/device_type
19 Description: This file shows the device type. This is one of the UFS
21 the descriptor could be found at UFS specifications 2.1.
26 What: /sys/bus/platform/devices/*.ufs/device_descriptor/device_class
29 Description: This file shows the device class. This is one of the UFS
31 the descriptor could be found at UFS specifications 2.1.
36 What: /sys/bus/platform/devices/*.ufs/device_descriptor/device_sub_class
[all …]
/Documentation/admin-guide/
Dufs.rst2 Using UFS
5 mount -t ufs -o ufstype=type_of_ufs device dir
8 UFS Options
12 UFS is a file system widely used in different operating systems.
15 type of ufs automatically. That's why user must specify type of
16 ufs manually by mount option ufstype. Possible values are:
19 old format of ufs
67 Any ufs bug report you can send to daniel.pirkl@email.cz or
/Documentation/devicetree/bindings/clock/
Dqcom,sa8775p-gcc.yaml26 - description: UFS memory first RX symbol clock
27 - description: UFS memory second RX symbol clock
28 - description: UFS memory first TX symbol clock
29 - description: UFS card first RX symbol clock
30 - description: UFS card second RX symbol clock
31 - description: UFS card first TX symbol clock
Dqcom,gcc-sm8350.yaml28 - description: UFS card Rx symbol 0 clock source (Optional clock)
29 - description: UFS card Rx symbol 1 clock source (Optional clock)
30 - description: UFS card Tx symbol 0 clock source (Optional clock)
31 - description: UFS phy Rx symbol 0 clock source (Optional clock)
32 - description: UFS phy Rx symbol 1 clock source (Optional clock)
33 - description: UFS phy Tx symbol 0 clock source (Optional clock)
Dqcom,gcc-apq8084.yaml32 - description: UFS RX symbol 0 clock
33 - description: UFS RX symbol 1 clock
34 - description: UFS TX symbol 0 clock
35 - description: UFS TX symbol 1 clock
60 /* UFS PHY on APQ8084 is not supported (yet), so these bindings just serve an example */
Dqcom,gcc-sc8280xp.yaml26 - description: UFS memory first RX symbol clock
27 - description: UFS memory second RX symbol clock
28 - description: UFS memory first TX symbol clock
29 - description: UFS card first RX symbol clock
30 - description: UFS card second RX symbol clock
31 - description: UFS card first TX symbol clock
Dqcom,sm4450-gcc.yaml27 - description: UFS Phy Rx symbol 0 clock source
28 - description: UFS Phy Rx symbol 1 clock source
29 - description: UFS Phy Tx symbol 0 clock source
Dqcom,sm8550-gcc.yaml29 - description: UFS Phy Rx symbol 0 clock source
30 - description: UFS Phy Rx symbol 1 clock source
31 - description: UFS Phy Tx symbol 0 clock source
Dqcom,gcc-msm8996.yaml33 - description: UFS RX symbol 0 clock (optional)
34 - description: UFS RX symbol 1 clock (optional)
35 - description: UFS TX symbol 0 clock (optional)
Dqcom,sm8650-gcc.yaml30 - description: UFS Phy Rx symbol 0 clock source
31 - description: UFS Phy Rx symbol 1 clock source
32 - description: UFS Phy Tx symbol 0 clock source
Dqcom,gcc-sm8450.yaml29 - description: UFS Phy Rx symbol 0 clock source (Optional clock)
30 - description: UFS Phy Rx symbol 1 clock source (Optional clock)
31 - description: UFS Phy Tx symbol 0 clock source (Optional clock)

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