Searched full:ulpi (Results 1 – 22 of 22) sorted by relevance
| /Documentation/devicetree/bindings/usb/ |
| D | ulpi.txt | 1 ULPI bus binding
4 Phys that are behind a ULPI connection can be described with the following
5 binding. The host controller shall have a "ulpi" named node as a child, and
6 that node shall have one enabled node underneath it representing the ulpi
15 ulpi {
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| D | fsl,usb2.yaml | 38 enum: [ulpi, serial, utmi, utmi_wide]
81 phy_type = "ulpi";
94 phy_type = "ulpi";
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| D | usb.yaml | 39 pin interface if ULPI is specified, Serial core/PHY interconnect if
44 enum: [utmi, utmi_wide, ulpi, serial, hsic]
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| D | snps,dwc3.yaml | 60 SoC Bus Clock (AHB/AXI/Native). ref generates ITP when the UTMI/ULPI
266 of resume. This option is to support certain legacy ULPI PHYs.
269 snps,ulpi-ext-vbus-drv:
271 Some ULPI USB PHY does not support internal VBUS supply, and driving
272 the CPEN pin, requires the configuration of the ulpi DRVVBUSEXTERNAL
289 High-Speed PHY interface selection between UTMI+ and ULPI when the
292 enum: [utmi, ulpi]
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| D | microchip,mpfs-musb.yaml | 39 Some ULPI USB PHYs do not support an internal VBUS supply and driving
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| D | twlxxxx-usb.txt | 31 specifies "ULPI" mode and "2" specifies "CEA2011_3PIN" mode.
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| D | omap-usb.txt | 13 specifying ULPI and UTMI respectively.
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| D | ci-hdrc-usb2.yaml | 73 ulpi:
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| D | dwc3-xilinx.yaml | 76 description: GPIO used for the reset ulpi-phy
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| /Documentation/devicetree/bindings/phy/ |
| D | nvidia,tegra20-usb-phy.yaml | 45 - description: ULPI PHY clock
67 - const: ulpi-link
105 enum: [utmi, ulpi, hsic]
293 const: ulpi
317 - const: ulpi-link
364 phy_type = "ulpi";
368 clock-names = "reg", "pll_u", "ulpi-link";
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| D | qcom,usb-hs-phy.yaml | 78 Sequence of ULPI address and value pairs to
102 ulpi {
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| D | nvidia,tegra124-xusb-padctl.yaml | 23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
145 ulpi:
153 ulpi-0:
434 ulpi-0:
555 ulpi {
557 ulpi-0 {
634 ulpi-0 {
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| D | phy-cpcap-usb.txt | 25 pinctrl-names = "default", "ulpi", "utmi", "uart";
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| D | nvidia,tegra186-xusb-padctl.yaml | 23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
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| D | nvidia,tegra194-xusb-padctl.yaml | 23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
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| D | nvidia,tegra210-xusb-padctl.yaml | 23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
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| /Documentation/devicetree/bindings/mfd/ |
| D | omap-usb-host.txt | 32 - single-ulpi-bypass: Must be present if the controller contains a single
33 ULPI bypass control bit. e.g. OMAP3 silicon <= ES2.1
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | nvidia,tegra20-pinmux.yaml | 67 spi4, trace, twc, uarta, uartb, uartc, uartd, uarte, ulpi,
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| D | nvidia,tegra114-pinmux.yaml | 95 spi6, sysclk, trace, uarta, uartb, uartc, uartd, ulpi, usb,
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| D | nvidia,tegra30-pinmux.yaml | 117 trace, uarta, uartb, uartc, uartd, uarte, ulpi, vgp1, vgp2,
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| D | nvidia,tegra124-xusb-padctl.txt | 71 - ulpi-0, hsic-0, hsic-1:
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| D | nvidia,tegra124-pinmux.yaml | 110 uartb, uartc, uartd, ulpi, usb, vgp1, vgp2, vgp3, vgp4, vgp5,
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