Searched +full:v +full:- +full:bit (Results 1 – 25 of 215) sorted by relevance
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| /Documentation/arch/riscv/ |
| D | vector.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Vector Extension Support for RISC-V Linux
8 order to support the use of the RISC-V Vector Extension.
11 ---------------------
15 these interfaces is to give init systems a way to modify the availability of V
19 are not portable to non-Linux, nor non-RISC-V environments, so it is discourage
20 to use in a portable code. To get the availability of V in an ELF program,
21 please read :c:macro:`COMPAT_HWCAP_ISA_V` bit of :c:macro:`ELF_HWCAP` in the
27 argument consists of two 2-bit enablement statuses and a bit for inheritance
30 Enablement status is a tri-state value each occupying 2-bit of space in
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| D | hwprobe.rst | 1 .. SPDX-License-Identifier: GPL-2.0
3 RISC-V Hardware Probing Interface
4 ---------------------------------
6 The RISC-V hardware probing interface is based around a single syscall, which
18 The arguments are split into three groups: an array of key-value pairs, a CPU
19 set, and some flags. The key-value pairs are supplied with a count. Userspace
22 will be cleared to -1, and its value set to 0. The CPU set is defined by
23 CPU_SET(3) with size ``cpusetsize`` bytes. For value-like keys (eg. vendor,
25 have the same value. Otherwise -1 will be returned. For boolean-like keys, the
33 by sys_riscv_hwprobe() to only those which match each of the key-value pairs.
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| D | vm-layout.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Virtual Memory Layout on RISC-V Linux
10 This document describes the virtual memory layout used by the RISC-V Linux
13 RISC-V Linux Kernel 32bit
16 RISC-V Linux Kernel SV32
17 ------------------------
21 RISC-V Linux Kernel 64bit
24 The RISC-V privileged architecture document states that the 64bit addresses
25 "must have bits 63–48 all equal to bit 47, or else a page-fault exception will
28 the RISC-V Linux Kernel resides.
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| /Documentation/hwmon/ |
| D | smsc47m192.rst | 10 Addresses scanned: I2C 0x2c - 0x2d
23 - Hartmut Rick <linux@rick.claranet.de>
25 - Special thanks to Jean Delvare for careful checking
30 -----------
33 of the SMSC LPC47M192 and compatible Super-I/O chips.
42 Voltages and temperatures are measured by an 8-bit ADC, the resolution
43 of the temperatures is 1 bit per degree C.
46 each voltage channel is 0V ... 255/192*(nominal voltage), the resolution
47 is 1 bit per (nominal voltage)/192.
51 The +12V analog voltage input channel (in4_input) is multiplexed with
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| D | adm1025.rst | 10 Addresses scanned: I2C 0x2c - 0x2e
18 Addresses scanned: I2C 0x2c - 0x2d
24 * Only two possible addresses (0x2c - 0x2d).
29 - Chen-Yuan Wu <gwu@esoft.com>,
30 - Jean Delvare <jdelvare@suse.de>
33 -----------
36 monitor for microprocessor-based systems, providing measurement and limit
38 are provided, for monitoring +2.5V, +3.3V, +5V and +12V power supplies and
39 the processor core voltage. The ADM1025 can monitor a sixth power-supply
41 remote temperature-sensing diode and an on-chip temperature sensor allows
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| D | max197.rst | 14 Datasheet: http://datasheets.maxim-ic.com/en/ds/MAX197.pdf
20 Datasheet: http://datasheets.maxim-ic.com/en/ds/MAX199.pdf
23 -----------
25 The A/D converters MAX197, and MAX199 are both 8-Channel, Multi-Range, 5V,
26 12-Bit DAS with 8+4 Bus Interface and Fault Protection.
28 The available ranges for the MAX197 are {0,-5V} to 5V, and {0,-10V} to 10V,
29 while they are {0,-2V} to 2V, and {0,-4V} to 4V on the MAX199.
32 -------------
40 On success, the function must return the 12-bit raw value read from the chip,
46 Bit Name Description
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| D | da9055.rst | 14 -----------
24 - Channel 0: VDDOUT - measurement of the system voltage
25 - Channel 1: ADC_IN1 - high impedance input (0 - 2.5V)
26 - Channel 2: ADC_IN2 - high impedance input (0 - 2.5V)
27 - Channel 3: ADC_IN3 - high impedance input (0 - 2.5V)
28 - Channel 4: Internal Tjunc. - sense (internal temp. sensor)
34 ------------------
37 are stored in a 10 bit ADC.
48 ----------------------
50 Temperatures are sampled by a 10 bit ADC. Junction temperatures
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| D | w83781d.rst | 10 Addresses scanned: I2C 0x28 - 0x2f, ISA 0x290 (8 I/O ports)
12 Datasheet: http://www.winbond-usa.com/products/winbond_products/pdfs/PCIC/w83781d.pdf
18 Addresses scanned: I2C 0x28 - 0x2f, ISA 0x290 (8 I/O ports)
28 Datasheet: http://www.winbond-usa.com/products/winbond_products/pdfs/PCIC/w83783s.pdf
34 Addresses scanned: I2C 0x28 - 0x2f
42 - Frodo Looijaard <frodol@dds.nl>,
43 - Philip Edelbrock <phil@netroedge.com>,
44 - Mark Studebaker <mdsxyz123@yahoo.com>
47 -----------------
67 -----------
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| D | bt1-pvt.rst | 1 .. SPDX-License-Identifier: GPL-2.0-only
3 Kernel driver bt1-pvt
8 * Baikal-T1 PVT sensor (in SoC)
10 Prefix: 'bt1-pvt'
12 Addresses scanned: -
21 -----------
24 embedded into Baikal-T1 process, voltage and temperature sensors. PVT IP-core
29 compile-time configurable due to the hardware interface implementation
40 in alarm-less configuration the data conversion is performed by the driver
41 on demand when read operation is requested via corresponding _input-file.
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| D | adm9240.rst | 10 Addresses scanned: I2C 0x2c - 0x2f
20 Addresses scanned: I2C 0x2c - 0x2f
24 http://pdfserv.maxim-ic.com/en/ds/DS1780.pdf
30 Addresses scanned: I2C 0x2c - 0x2f
37 - Frodo Looijaard <frodol@dds.nl>,
38 - Philip Edelbrock <phil@netroedge.com>,
39 - Michiel Rook <michiel@grendelproject.nl>,
40 - Grant Coady <gcoady.lk@gmail.com> with guidance
44 ---------
46 chip MSB 5-bit address. Each chip reports a unique manufacturer
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| D | vt1211.rst | 10 Addresses scanned: none, address read from Super-I/O config space
24 -----------------
29 configuration for channels 1-5.
30 Legal values are in the range of 0-31. Bit 0 maps to
31 UCH1, bit 1 maps to UCH2 and so on. Setting a bit to 1
33 setting a bit to 0 enables the voltage input.
47 -----------
49 The VIA VT1211 Super-I/O chip includes complete hardware monitoring
52 implements 5 universal input channels (UCH1-5) that can be individually
60 connected to the PWM outputs of the VT1211 :-().
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| D | f71805f.rst | 44 -----------
57 The Fintek F71806F/FG Super-I/O chip is essentially the same as the
65 ------------------
67 Voltages are sampled by an 8-bit ADC with a LSB of 8 mV. The supported
68 range is thus from 0 to 2.040 V. Voltage values outside of this range
70 the chip's own power source (+3.3V), and is divided internally by a
83 in0 VCC VCC3.3V int. int. 2.00 1.65 V
84 in1 VIN1 VTT1.2V 10K - 1.00 1.20 V
85 in2 VIN2 VRAM 100K 100K 2.00 ~1.25 V [1]_
86 in3 VIN3 VCHIPSET 47K 100K 1.47 2.24 V [2]_
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| D | dme1737.rst | 18 Addresses scanned: none, address read from Super-I/O config space
34 Addresses scanned: none, address read from Super-I/O config space
43 -----------------
52 Include non-standard LPC addresses 0x162e and 0x164e
55 - VIA EPIA SN18000
59 -----------
63 and SCH5127 Super-I/O chips. These chips feature monitoring of 3 temp sensors
64 temp[1-3] (2 remote diodes and 1 internal), 8 voltages in[0-7] (7 external and
65 1 internal) and up to 6 fan speeds fan[1-6]. Additionally, the chips implement
66 up to 5 PWM outputs pwm[1-3,5-6] for controlling fan speeds both manually and
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| /Documentation/userspace-api/media/v4l/ |
| D | pixfmt-packed-hsv.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _packed-hsv:
13 depends on the hsv-encoding used, see :ref:`colorspaces`.
14 The *saturation* (s) and the *value* (v) are measured in percentage of the
18 The values are packed in 24 or 32 bit formats.
29 .. _packed-hsv-formats:
31 .. flat-table:: Packed HSV Image Formats
32 :header-rows: 2
33 :stub-columns: 0
35 * - Identifier
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| D | subdev-formats.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _v4l2-mbus-format:
14 .. flat-table:: struct v4l2_mbus_framefmt
15 :header-rows: 0
16 :stub-columns: 0
19 * - __u32
20 - ``width``
21 - Image width in pixels.
22 * - __u32
23 - ``height``
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| /Documentation/virt/hyperv/ |
| D | overview.rst | 1 .. SPDX-License-Identifier: GPL-2.0
6 enlightened guest on Microsoft's Hyper-V hypervisor. Hyper-V
7 consists primarily of a bare-metal hypervisor plus a virtual machine
10 partitions. In this documentation, references to Hyper-V usually
15 Hyper-V runs on x86/x64 and arm64 architectures, and Linux guests
16 are supported on both. The functionality and behavior of Hyper-V is
19 Linux Guest Communication with Hyper-V
20 --------------------------------------
21 Linux guests communicate with Hyper-V in four different ways:
24 some guest actions trap to Hyper-V. Hyper-V emulates the action and
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| D | clocks.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 -----
8 On arm64, Hyper-V virtualizes the ARMv8 architectural system counter
12 architectural system counter is functional in guest VMs on Hyper-V.
13 While Hyper-V also provides a synthetic system clock and four synthetic
14 per-CPU timers as described in the TLFS, they are not used by the
15 Linux kernel in a Hyper-V guest on arm64. However, older versions
16 of Hyper-V for arm64 only partially virtualize the ARMv8
19 Linux kernel versions on these older Hyper-V versions requires an
20 out-of-tree patch to use the Hyper-V synthetic clocks/timers instead.
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| /Documentation/arch/powerpc/ |
| D | cpu_families.rst | 10 ------------------
12 - Hash MMU (except 603 and e300)
13 - Radix MMU (POWER9 and later)
14 - Software loaded TLB (603 and e300)
15 - Selectable Software loaded TLB in addition to hash MMU (755, 7450, e600)
16 - Mix of 32 & 64 bit::
18 +--------------+ +----------------+
19 | Old POWER | --------------> | RS64 (threads) |
20 +--------------+ +----------------+
23 v
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| /Documentation/devicetree/bindings/riscv/ |
| D | extensions.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
36 Identifies the specific RISC-V instruction set architecture
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | sprd,pinctrl.txt | 6 register contains several bit fields with one bit or several bits
9 driving level": One pin can output 3.0v or 1.8v, depending on the
11 select 3.0v, then the pin can output 3.0v. "system control" is used
16 of them, so we can not make every Spreadtrum-special configuration
22 Moreover we recognise every fields comprising one bit or several
24 record every pin's bit offset, bit width and register offset to
35 - input-enable
36 - input-disable
37 - output-high
38 - output-low
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| D | fsl,mxs-pinctrl.txt | 6 voltage and pull-up.
9 - compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
10 - reg: Should contain the register physical address and length for the
13 Please refer to pinctrl-bindings.txt in this directory for details of the
20 information about pull-up. For this reason, even seemingly boolean values are
34 particular function, like SSP0 functioning as mmc0-8bit. That said, the
37 "pinctrl-*" phandle in client device node should only have one group node
41 Required subnode-properties:
42 - fsl,pinmux-ids: An integer array. Each integer in the array specify a pin
56 - reg: Should be the index of the group nodes for same function. This property
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | adi,ad7091r5.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AD7091R-2/-4/-5/-8 Multi-Channel 12-Bit ADCs
10 - Michael Hennerich <michael.hennerich@analog.com>
11 - Marcelo Schmitt <marcelo.schmitt@analog.com>
14 Analog Devices AD7091R5 4-Channel 12-Bit ADC supporting I2C interface
15 https://www.analog.com/media/en/technical-documentation/data-sheets/ad7091r-5.pdf
16 Analog Devices AD7091R-2/AD7091R-4/AD7091R-8 2-/4-/8-Channel 12-Bit ADCs
18 https://www.analog.com/media/en/technical-documentation/data-sheets/AD7091R-2_7091R-4_7091R-8.pdf
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| /Documentation/devicetree/bindings/sound/ |
| D | ak5386.txt | 1 AK5386 Single-ended 24-Bit 192kHz delta-sigma ADC
7 - compatible : "asahi-kasei,ak5386"
11 - reset-gpio : a GPIO spec for the reset/power down pin.
13 - va-supply : a regulator spec, providing 5.0V
14 - vd-supply : a regulator spec, providing 3.3V
19 compatible = "asahi-kasei,ak5386";
20 reset-gpio = <&gpio0 23>;
21 va-supply = <&vdd_5v0_reg>;
22 vd-supply = <&vdd_3v3_reg>;
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| /Documentation/devicetree/bindings/phy/ |
| D | qcom,qusb2-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Wesley Cheng <quic_wcheng@quicinc.com>
19 - items:
20 - enum:
21 - qcom,ipq6018-qusb2-phy
22 - qcom,ipq8074-qusb2-phy
23 - qcom,ipq9574-qusb2-phy
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| /Documentation/devicetree/bindings/leds/backlight/ |
| D | richtek,rt4831-backlight.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/backlight/richtek,rt4831-backlight.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
20 https://www.richtek.com/assets/product_file/RT4831A/DS4831A-05.pdf
23 - $ref: common.yaml#
27 const: richtek,rt4831-backlight
29 default-brightness:
33 max-brightness:
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