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/Documentation/virt/hyperv/
Doverview.rst6 enlightened guest on Microsoft's Hyper-V hypervisor. Hyper-V
10 partitions. In this documentation, references to Hyper-V usually
15 Hyper-V runs on x86/x64 and arm64 architectures, and Linux guests
16 are supported on both. The functionality and behavior of Hyper-V is
19 Linux Guest Communication with Hyper-V
21 Linux guests communicate with Hyper-V in four different ways:
24 some guest actions trap to Hyper-V. Hyper-V emulates the action and
29 Hyper-V, passing parameters. Hyper-V performs the requested action
32 Hyper-V. On x86/x64, hypercalls use a Hyper-V specific calling
36 * Synthetic register access: Hyper-V implements a variety of
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Dclocks.rst8 On arm64, Hyper-V virtualizes the ARMv8 architectural system counter
12 architectural system counter is functional in guest VMs on Hyper-V.
13 While Hyper-V also provides a synthetic system clock and four synthetic
15 Linux kernel in a Hyper-V guest on arm64. However, older versions
16 of Hyper-V for arm64 only partially virtualize the ARMv8
19 Linux kernel versions on these older Hyper-V versions requires an
20 out-of-tree patch to use the Hyper-V synthetic clocks/timers instead.
24 On x86/x64, Hyper-V provides guest VMs with a synthetic system clock
25 and four synthetic per-CPU timers as described in the TLFS. Hyper-V
29 Hyper-V performs TSC calibration, and provides the TSC frequency
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Dvpci.rst5 In a Hyper-V guest VM, PCI pass-thru devices (also called
16 Hyper-V terminology for vPCI devices is "Discrete Device
17 Assignment" (DDA). Public documentation for Hyper-V DDA is
20 .. _DDA: https://learn.microsoft.com/en-us/windows-server/virtualization/hyper-v/plan/plan-for-depl…
25 driver to interact directly with the hardware. See Hyper-V
35 Hyper-V provides full PCI functionality for a vPCI device when
40 its integration with the Linux PCI subsystem must use Hyper-V
41 specific mechanisms. Consequently, vPCI devices on Hyper-V
62 VMBus connection to the vPCI VSP on the Hyper-V host. That
76 PCI device setup follows a sequence that Hyper-V originally
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Dvmbus.rst5 VMBus is a software construct provided by Hyper-V to guest VMs. It
7 devices that Hyper-V presents to guest VMs. The control path is
11 and the synthetic device implementation that is part of Hyper-V, and
12 signaling primitives to allow Hyper-V and the guest to interrupt
17 establishes the VMBus control path with the Hyper-V host, then
21 Most synthetic devices offered by Hyper-V have a corresponding Linux
34 * Key/Value Pair (KVP) exchange with Hyper-V
35 * Hyper-V online backup (a.k.a. VSS)
41 Hyper-V that are used only by Windows guests and for which Linux
44 Hyper-V uses the terms "VSP" and "VSC" in describing synthetic
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/Documentation/hwmon/
Dmc13783-adc.rst47 0 Battery Voltage (BATT) 2.50 - 4.65V -2.40V
49 2 Application Supply (BP) 2.50 - 4.65V -2.40V
50 3 Charger Voltage (CHRGRAW) 0 - 10V / /5
51 0 - 20V /10
52 4 Charger Current (CHRGISNSP-CHRGISNSN) -0.25 - 0.25V x4
53 5 General Purpose ADIN5 / Battery Pack Thermistor 0 - 2.30V No
54 6 General Purpose ADIN6 / Backup Voltage (LICELL) 0 - 2.30V / No /
55 1.50 - 3.50V -1.20V
56 7 General Purpose ADIN7 / UID / Die Temperature 0 - 2.30V / No /
57 0 - 2.55V / x0.9 / No
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Dltc4245.rst52 in1_input 12v input voltage (mV)
53 in2_input 5v input voltage (mV)
54 in3_input 3v input voltage (mV)
55 in4_input Vee (-12v) input voltage (mV)
57 in1_min_alarm 12v input undervoltage alarm
58 in2_min_alarm 5v input undervoltage alarm
59 in3_min_alarm 3v input undervoltage alarm
60 in4_min_alarm Vee (-12v) input undervoltage alarm
62 curr1_input 12v current (mA)
63 curr2_input 5v current (mA)
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Ddme1737.rst94 in0: +5VTR (+5V standby) 0V - 6.64V
95 in1: Vccp (processor core) 0V - 3V
96 in2: VCC (internal +3.3V) 0V - 4.38V
97 in3: +5V 0V - 6.64V
98 in4: +12V 0V - 16V
99 in5: VTR (+3.3V standby) 0V - 4.38V
100 in6: Vbat (+3.0V) 0V - 4.38V
104 in0: +2.5V 0V - 3.32V
105 in1: Vccp (processor core) 0V - 2V
106 in2: VCC (internal +3.3V) 0V - 4.38V
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Dcorsair-psu.rst51 curr2_input Current on the 12v psu rail
52 curr2_crit Current max critical value on the 12v psu rail
53 curr3_input Current on the 5v psu rail
54 curr3_crit Current max critical value on the 5v psu rail
55 curr4_input Current on the 3.3v psu rail
56 curr4_crit Current max critical value on the 3.3v psu rail
59 in1_input Voltage of the 12v psu rail
60 in1_crit Voltage max critical value on the 12v psu rail
61 in1_lcrit Voltage min critical value on the 12v psu rail
62 in2_input Voltage of the 5v psu rail
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Df71805f.rst68 range is thus from 0 to 2.040 V. Voltage values outside of this range
70 the chip's own power source (+3.3V), and is divided internally by a
83 in0 VCC VCC3.3V int. int. 2.00 1.65 V
84 in1 VIN1 VTT1.2V 10K - 1.00 1.20 V
85 in2 VIN2 VRAM 100K 100K 2.00 ~1.25 V [1]_
86 in3 VIN3 VCHIPSET 47K 100K 1.47 2.24 V [2]_
87 in4 VIN4 VCC5V 200K 47K 5.25 0.95 V
88 in5 VIN5 +12V 200K 20K 11.00 1.05 V
89 in6 VIN6 VCC1.5V 10K - 1.00 1.50 V
90 in7 VIN7 VCORE 10K - 1.00 ~1.40 V [1]_
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/Documentation/devicetree/bindings/iio/dac/
Dadi,ltc2664.yaml14 Analog Devices LTC2664 4 channel, 12-/16-Bit, +-10V DAC
31 v-pos-supply:
34 v-neg-supply:
61 0 - MPS2=GND, MPS1=GND, MSP0=GND (+-10V, reset to 0V)
62 1 - MPS2=GND, MPS1=GND, MSP0=VCC (+-5V, reset to 0V)
63 2 - MPS2=GND, MPS1=VCC, MSP0=GND (+-2.5V, reset to 0V)
64 3 - MPS2=GND, MPS1=VCC, MSP0=VCC (0V to 10, reset to 0V)
65 4 - MPS2=VCC, MPS1=GND, MSP0=GND (0V to 10V, reset to 5V)
66 5 - MPS2=VCC, MPS1=GND, MSP0=VCC (0V to 5V, reset to 0V)
67 6 - MPS2=VCC, MPS1=VCC, MSP0=GND (0V to 5V, reset to 2.5V)
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/Documentation/devicetree/bindings/media/i2c/
Dsamsung,s5k5baf.yaml39 description: Analog power supply 2.8V (2.6V to 3.0V)
42 description: I/O power supply 1.8V (1.65V to 1.95V) or 2.8V (2.5V to 3.1V)
46 Regulator input power supply 1.8V (1.7V to 1.9V) or 2.8V (2.6V to 3.0)
Dthine,thp7312.yaml54 1.2V supply for core, PLL, MIPI rx and MIPI tx.
58 Supply for input (RX). 1.8V for MIPI, or 1.8/2.8/3.3V for parallel.
62 Supply for output (TX). 1.8V for MIPI, or 1.8/2.8/3.3V for parallel.
66 Supply for host interface. 1.8V, 2.8V, or 3.3V.
70 Supply for sensor interface. 1.8V, 2.8V, or 3.3V.
74 Supply for GPIO_0. 1.8V, 2.8V, or 3.3V.
78 Supply for GPIO_1. 1.8V, 2.8V, or 3.3V.
/Documentation/userspace-api/media/v4l/
Dpixfmt-packed-hsv.rst14 The *saturation* (s) and the *value* (v) are measured in percentage of the
112 - v\ :sub:`7`
113 - v\ :sub:`6`
114 - v\ :sub:`5`
115 - v\ :sub:`4`
116 - v\ :sub:`3`
117 - v\ :sub:`2`
118 - v\ :sub:`1`
119 - v\ :sub:`0`
143 - v\ :sub:`7`
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Dsubdev-formats.rst3290 and V components. Some formats include dummy bits in some of their
3297 - The Y, U and V components order code, as transferred on the bus.
3319 the U, Y, V, Y order will be named ``MEDIA_BUS_FMT_UYVY8_2X8``.
3333 - v\ :sub:`x` for red chroma component bit number x
3501 - v\ :sub:`7`
3502 - v\ :sub:`6`
3503 - v\ :sub:`5`
3504 - v\ :sub:`4`
3505 - v\ :sub:`3`
3506 - v\ :sub:`2`
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/Documentation/arch/riscv/
Dpatch-acceptance.rst8 The RISC-V instruction set architecture is developed in the open:
13 challenge for RISC-V Linux maintenance. Linux maintainers disapprove
16 principles to the RISC-V-related code that will be accepted for
22 RISC-V has a patchwork instance, where the status of patches can be checked:
26 If your patch does not appear in the default view, the RISC-V maintainers have
31 RISC-V `for-next` and `fixes` branches, depending on whether the patch has been
32 detected as a fix. Failing those, it will use the RISC-V `master` branch.
42 specifications from the RISC-V foundation this means "Frozen" or
47 Additionally, the RISC-V specification allows implementers to create
49 to go through any review or ratification process by the RISC-V
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Dhwprobe.rst3 RISC-V Hardware Probing Interface
6 The RISC-V hardware probing interface is based around a single syscall, which
49 as defined by the RISC-V privileged architecture specification.
52 defined by the RISC-V privileged architecture specification.
55 defined by the RISC-V privileged architecture specification.
76 minimumNumber/maximumNumber, not minNum/maxNum") of the RISC-V ISA manual.
79 by version 2.2 of the RISC-V ISA manual.
81 * :c:macro:`RISCV_HWPROBE_IMA_V`: The V extension is supported, as defined by
82 version 1.0 of the RISC-V Vector extension manual.
128 defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
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/Documentation/arch/powerpc/
Dcpu_families.rst23 v
29 v v
35 v v v
41 v v v
47 v v
53 v v
59 v v
65 v v v
71 v v v
77 v
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/Documentation/devicetree/bindings/sound/
Dcs35l32.txt25 3 = Boost voltage fixed at 5 V.
40 0 = 3.1V
41 1 = 3.2V
42 2 = 3.3V (Default)
43 3 = 3.4V
46 0 = 3.1V
47 1 = 3.2V
48 2 = 3.3V
49 3 = 3.4V (Default)
50 4 = 3.5V
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Dti,ts3a227e.yaml34 - 0 # 2.1 V
35 - 1 # 2.2 V
36 - 2 # 2.3 V
37 - 3 # 2.4 V
38 - 4 # 2.5 V
39 - 5 # 2.6 V
40 - 6 # 2.7 V
41 - 7 # 2.8 V
/Documentation/litmus-tests/atomic/
DAtomic-RMW-ops-are-atomic-WRT-atomic_set.litmus11 atomic_t v = ATOMIC_INIT(1);
14 P0(atomic_t *v)
16 (void)atomic_add_unless(v, 1, 0);
19 P1(atomic_t *v)
21 atomic_set(v, 0);
25 (v=2)
/Documentation/devicetree/bindings/regulator/
Dltc3589.txt21 0.3625 V to 0.75 V in 12.5 mV steps. The output voltage thus ranges between
22 0.3625 * (1 + R1/R2) V and 0.75 * (1 + R1/R2) V. Regulators bb-out and ldo1
23 have a fixed 0.8 V reference and thus output 0.8 * (1 + R1/R2) V. The ldo3
24 regulator is fixed to 1.8 V on LTC3589 and to 2.8 V on LTC3589-1,2. The ldo4
25 regulator can output between 1.8 V and 3.3 V on LTC3589 and between 1.2 V
26 and 3.2 V on LTC3589-1,2 in four steps. The ldo1 standby regulator can not
/Documentation/devicetree/bindings/timer/
Driscv,timer.yaml7 title: RISC-V timer
13 RISC-V platforms always have a RISC-V timer device for the supervisor-mode
14 based on the time CSR defined by the RISC-V privileged specification. The
15 timer interrupts of this device are configured using the RISC-V SBI Time
16 extension or the RISC-V Sstc extension.
18 The clock frequency of RISC-V timer device is specified via the
/Documentation/translations/it_IT/arch/riscv/
Dpatch-acceptance.rst12 L'insieme di istruzioni RISC-V sono sviluppate in modo aperto: le
18 supporto RISC-V nel kernel Linux. I manutentori Linux non amano
22 relativo all'architettura RISC-V che verrà accettato per l'inclusione
28 RISC-V ha un'istanza di patchwork dov'è possibile controllare lo stato delle patch:
32 Se la vostra patch non appare nella vista predefinita, i manutentori di RISC-V
38 riferimento HEAD corrente dei rami `for-next` e `fixes` dei sorgenti RISC-V,
40 caso contrario, utilizzerà il ramo `master` di RISC-V. L'esatto commit a cui è
49 RISC-V li classifica come "Frozen" o "Retified". (Ovviamente, gli
53 In aggiunta, la specifica RISC-V permette agli implementatori di
55 attraverso il processo di revisione della fondazione RISC-V. Per
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/Documentation/fb/
Dviafb.modes29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
116 # D: 52.406 MHz, H: 61.800 kHz, V: 120.00 Hz
137 # D: 26.880 MHz, H: 30.000 kHz, V: 60.24 Hz
158 # D: 29.500 MHz, H: 29.738 kHz, V: 60.00 Hz
179 # D: 32.668 MHz, H: 35.820 kHz, V: 60.00 Hz
200 # D: 40.00 MHz, H: 37.879 kHz, V: 60.32 Hz
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/Documentation/devicetree/bindings/display/bridge/
Dchipone,icn6211.yaml40 description: A 1.8V/2.5V/3.3V supply that power the MIPI RX.
43 description: A 1.8V/2.5V/3.3V supply that power the PLL.
46 description: A 1.8V/2.5V/3.3V supply that power the RGB output.

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