| /Documentation/devicetree/bindings/media/ |
| D | rockchip-vpu.yaml | 5 $id: http://devicetree.org/schemas/media/rockchip-vpu.yaml#
8 title: Hantro G1 VPU codecs implemented on Rockchip SoCs
20 - rockchip,rk3036-vpu
21 - rockchip,rk3066-vpu
22 - rockchip,rk3288-vpu
23 - rockchip,rk3328-vpu
24 - rockchip,rk3399-vpu
25 - rockchip,px30-vpu
26 - rockchip,rk3568-vpu
27 - rockchip,rk3588-av1-vpu
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| D | amphion,vpu.yaml | 5 $id: http://devicetree.org/schemas/media/amphion,vpu.yaml#
8 title: Amphion VPU codec IP
20 pattern: "^vpu@[0-9a-f]+$"
25 - nxp,imx8qm-vpu
26 - nxp,imx8qxp-vpu
45 Each vpu encoder or decoder correspond a MU, which used for communication
50 "^vpu-core@[0-9a-f]+$":
61 - nxp,imx8q-vpu-decoder
62 - nxp,imx8q-vpu-encoder
114 vpu: vpu@2c000000 {
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| D | mediatek-vpu.txt | 7 - compatible: "mediatek,mt8173-vpu"
14 - clock-names: must be main. It is the main clock of VPU
19 to be used for VPU extended memory; if not present, VPU may be located
23 vpu: vpu@10020000 {
24 compatible = "mediatek,mt8173-vpu";
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| D | nxp,imx8mq-vpu.yaml | 5 $id: http://devicetree.org/schemas/media/nxp,imx8mq-vpu.yaml#
8 title: Hantro G1/G2 VPU codecs implemented on i.MX8M SoCs
19 - const: nxp,imx8mq-vpu
21 - const: nxp,imx8mq-vpu-g1
22 - const: nxp,imx8mq-vpu-g2
23 - const: nxp,imx8mm-vpu-g1
52 compatible = "nxp,imx8mq-vpu-g1";
64 compatible = "nxp,imx8mq-vpu-g2";
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| D | coda.yaml | 14 called VPU (Video Processing Unit).
20 - const: fsl,imx27-vpu
23 - const: fsl,imx51-vpu
26 - const: fsl,imx53-vpu
30 - fsl,imx6dl-vpu
31 - fsl,imx6q-vpu
100 vpu: video-codec@63ff4000 {
101 compatible = "fsl,imx53-vpu", "cnm,coda7541";
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| D | allwinner,sun50i-h6-vpu-g2.yaml | 5 $id: http://devicetree.org/schemas/media/allwinner,sun50i-h6-vpu-g2.yaml#
8 title: Hantro G2 VPU codec implemented on Allwinner H6 SoC
18 const: allwinner,sun50i-h6-vpu-g2
60 compatible = "allwinner,sun50i-h6-vpu-g2";
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| D | mediatek,vcodec-encoder.yaml | 56 mediatek,vpu:
59 Describes point to vpu.
110 - mediatek,vpu
161 mediatek,vpu = <&vpu>;
181 mediatek,vpu = <&vpu>;
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| D | mediatek-mdp.txt | 7 - mediatek,vpu: the node of video processor unit, see
8 Documentation/devicetree/bindings/media/mediatek-vpu.txt for details.
40 mediatek,vpu = <&vpu>;
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| D | mediatek,vcodec-decoder.yaml | 68 mediatek,vpu:
71 Describes point to vpu.
121 - mediatek,vpu
171 mediatek,vpu = <&vpu>;
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| D | cnm,wave521c.yaml | 42 The VPU uses the SRAM to store some of the reference data instead of
55 vpu: video-codec@12345678 {
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| D | brcm,bcm2835-unicam.yaml | 44 - description: Clock for the VPU (core clock).
49 - const: vpu
116 clock-names = "lp", "vpu";
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| D | fsl-vdoa.txt | 6 960 VPU to the conventional raster-scan order for scanout.
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| D | microchip,sama5d4-vdec.yaml | 8 title: Hantro G1 VPU codec implemented on Microchip SAMA5D4 SoCs
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| D | rockchip,rk3568-vepu.yaml | 8 title: Hantro G1 VPU encoders implemented on Rockchip SoCs
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | ingenic,vpu.yaml | 4 $id: http://devicetree.org/schemas/remoteproc/ingenic,vpu.yaml#
10 Inside the Video Processing Unit (VPU) of the recent JZ47xx SoCs from
20 const: ingenic,jz4770-vpu-rproc
39 - description: vpu clock
44 - const: vpu
63 vpu: video-decoder@132a0000 {
64 compatible = "ingenic,jz4770-vpu-rproc";
73 clock-names = "aux", "vpu";
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| /Documentation/devicetree/bindings/soc/imx/ |
| D | fsl,imx8mq-vpu-blk-ctrl.yaml | 4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml#
7 title: NXP i.MX8MQ VPU blk-ctrl
13 The i.MX8MQ VPU blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the VPU peripherals
15 located in the VPU domain of the SoC.
20 - const: fsl,imx8mq-vpu-blk-ctrl
63 compatible = "fsl,imx8mq-vpu-blk-ctrl";
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| D | fsl,imx8mm-vpu-blk-ctrl.yaml | 4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml#
7 title: NXP i.MX8MM VPU blk-ctrl
13 The i.MX8MM VPU blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the VPU peripherals
15 located in the VPU domain of the SoC.
20 - const: fsl,imx8mm-vpu-blk-ctrl
60 const: fsl,imx8mm-vpu-blk-ctrl
105 const: fsl,imx8mp-vpu-blk-ctrl
154 compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
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| /Documentation/devicetree/bindings/power/ |
| D | amlogic,meson-gx-pwrc.txt | 6 VPU Power Domain
20 - "amlogic,meson-gx-pwrc-vpu" for the Meson GX SoCs
21 - "amlogic,meson-g12a-pwrc-vpu" for the Meson G12A SoCs
26 - clocks: from common clock binding: handle to VPU and VAPB clocks
27 - clock-names: from common clock binding: must contain "vpu", "vapb"
41 pwrc_vpu: power-controller-vpu {
42 compatible = "amlogic,meson-gx-pwrc-vpu";
59 clock-names = "vpu", "vapb";
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| D | amlogic,meson-ee-pwrc.yaml | 41 - const: vpu
183 clock-names = "vpu", "vapb";
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| /Documentation/devicetree/bindings/display/ |
| D | amlogic,meson-vpu.yaml | 5 $id: http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#
17 DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
63 - amlogic,meson-gxbb-vpu # GXBB (S905)
64 - amlogic,meson-gxl-vpu # GXL (S905X, S905D)
65 - amlogic,meson-gxm-vpu # GXM (S912)
66 - const: amlogic,meson-gx-vpu
68 - amlogic,meson-g12a-vpu # G12A (S905X2, S905Y2, S905D2)
75 - const: vpu
124 vpu: vpu@d0100000 {
125 compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
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| D | amlogic,meson-dw-hdmi.yaml | 36 Pixel data arrives in "4:4:4" format from the VENC block and the VPU HDMI mux
140 /* VPU VENC Input */
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| /Documentation/devicetree/bindings/clock/ |
| D | nxp,imx95-blk-ctl.yaml | 20 - nxp,imx95-vpu-csr
51 compatible = "nxp,imx95-vpu-csr", "syscon";
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| /Documentation/devicetree/bindings/soc/bcm/ |
| D | brcm,bcm2835-vchiq.yaml | 14 to communicate with the VPU-side OS services.
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| /Documentation/admin-guide/media/ |
| D | platform-cardlist.rst | 26 coda-vpu Chips&Media Coda multi-standard codec IP
39 mtk-vpu Mediatek Video Processor Unit
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| /Documentation/devicetree/bindings/reset/ |
| D | fsl,imx-src.yaml | 13 The system reset controller can be used to reset the GPU, VPU,
|