Searched full:vector (Results 1 – 25 of 127) sorted by relevance
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| /Documentation/arch/arm64/ |
| D | sme.rst | 21 * PSTATE.SM, PSTATE.ZA, the streaming mode vector length, the ZA and (when
24 * The presence of SME is reported to userspace via HWCAP2_SME in the aux vector
30 aux vector AT_HWCAP2 entry. Presence of this flag implies the presence of
75 2. Vector lengths
78 SME defines a second vector length similar to the SVE vector length which
81 mode SVE vector.
109 * All other SME state of a thread, including the currently configured vector
110 length, the state of the PR_SME_VL_INHERIT flag, and the deferred vector
127 the thread's vector length (in za_context.vl).
167 * The vector length cannot be changed via signal return. If za_context.vl in
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| D | sve.rst | 2 Scalable Vector Extension support for AArch64 Linux
10 order to support use of the ARM Scalable Vector Extension (SVE), including
25 * SVE registers Z0..Z31, P0..P15 and FFR and the current vector length VL, are
32 * The presence of SVE is reported to userspace via HWCAP_SVE in the aux vector
46 be reported in the AT_HWCAP2 aux vector entry. In addition to this,
64 reported in the AT_HWCAP2 aux vector entry. Among other things SME adds
66 separate SME vector length and the same Z/V registers. See sme.rst
90 2. Vector length terminology
93 The size of an SVE vector (Z) register is referred to as the "vector length".
95 To avoid confusion about the units used to express vector length, the kernel
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| /Documentation/arch/riscv/ |
| D | vector.rst | 4 Vector Extension Support for RISC-V Linux
8 order to support the use of the RISC-V Vector Extension.
14 status for the use of Vector in userspace. The intended usage guideline for
22 auxiliary vector.
26 Sets the Vector enablement status of the calling thread, where the control
37 * :c:macro:`PR_RISCV_V_VSTATE_CTRL_ON`: Allow Vector to be run for the
40 * :c:macro:`PR_RISCV_V_VSTATE_CTRL_OFF`: Disallow Vector. Executing Vector
54 Vector enablement status for the calling thread. The calling thread is
55 not able to turn off Vector once it has been enabled. The prctl() call
62 Vector enablement setting for the calling thread at the next execve()
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| D | hwprobe.rst | 82 version 1.0 of the RISC-V Vector extension manual.
167 defined in the RISC-V Vector manual starting from commit e2ccd0548d6c
171 defined in the RISC-V Vector manual starting from commit e2ccd0548d6c
195 * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is
196 supported, as defined by version 1.0 of the RISC-V Vector extension manual.
198 * :c:macro:`RISCV_HWPROBE_EXT_ZVE32F`: The Vector sub-extension Zve32f is
199 supported, as defined by version 1.0 of the RISC-V Vector extension manual.
201 * :c:macro:`RISCV_HWPROBE_EXT_ZVE64X`: The Vector sub-extension Zve64x is
202 supported, as defined by version 1.0 of the RISC-V Vector extension manual.
204 * :c:macro:`RISCV_HWPROBE_EXT_ZVE64F`: The Vector sub-extension Zve64f is
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| D | index.rst | 15 vector
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| /Documentation/devicetree/bindings/riscv/ |
| D | extensions.yaml | 114 The standard V extension for vector operations, as ratified
432 riscv-crypto-spec-vector.adoc") of riscv-crypto.
438 riscv-crypto-spec-vector.adoc") of riscv-crypto.
443 in commit 6f702a2 ("Vector extensions are now ratified") of
449 in commit 6f702a2 ("Vector extensions are now ratified") of
455 in commit 6f702a2 ("Vector extensions are now ratified") of
461 in commit 6f702a2 ("Vector extensions are now ratified") of
467 in commit 6f702a2 ("Vector extensions are now ratified") of
484 The standard Zvkb extension for vector cryptography bit-manipulation
486 riscv-crypto-spec-vector.adoc") of riscv-crypto.
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| /Documentation/filesystems/xfs/ |
| D | xfs-delayed-logging-design.rst | 465 vector array that points to the changed regions in the item. The log write code
469 allocated memory buffer big enough to fit the formatted vector.
471 If we then copy the vector into the memory buffer and rewrite the vector to
476 resulting in a vector that is transactionally consistent and can be accessed
484 Current format log vector::
487 Vector 1 +----+
488 Vector 2 +----+
489 Vector 3 +----------+
495 Delayed logging vector::
498 Vector 1 +----+
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| /Documentation/admin-guide/hw-vuln/ |
| D | gather_data_sampling.rst | 7 speculative access to data which was previously stored in vector registers.
12 are merged into the destination vector register. However, when a gather
14 architectural or internal vector registers may get transiently forwarded to the
15 destination vector register instead. This will allow a malicious attacker to
19 The attacker uses gather instructions to infer the stale vector register data.
20 The victim does not need to do anything special other than use the vector
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| /Documentation/arch/arm/ |
| D | memory.rst | 33 ffff0000 ffff0fff CPU vector page.
35 CPU supports vector relocation (control
89 00000000 00000fff CPU vector page / null pointer trap
90 CPUs which do not support vector remapping
91 place their vector page here. NULL pointer
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| /Documentation/images/ |
| D | COPYING-logo | 14 The SVG version was re-illustrated in vector by Garrett LeSage and
18 There are also black-and-white and inverted vector versions at
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| /Documentation/misc-devices/ |
| D | spear-pcie-gadget.rst | 43 number of MSI vector granted.
60 no_of_msi number of MSI vector needed.
62 send_msi write MSI vector to be sent.
142 if MSI is to be used as interrupt, program no of msi vector needed (say4)::
165 Should return 4 (number of requested MSI vector)
167 to send msi vector 2::
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| /Documentation/devicetree/bindings/mailbox/ |
| D | hisilicon,hi3660-mailbox.txt | 18 dst_irq : Remote interrupt vector
19 ack_irq : Local interrupt vector
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | st-rproc.txt | 20 - st,syscfg System configuration register which holds the boot vector
23 2nd cell: Boot vector register offset
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| /Documentation/ABI/testing/ |
| D | configfs-spear-pcie-gadget | 22 no_of_msi used to configure number of MSI vector needed and
25 send_msi write MSI vector to be sent.
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| /Documentation/arch/x86/x86_64/ |
| D | fred.rst | 44 vector, FRED requires the software to dispatch an event to its handler
45 based on both the event's type and vector. Therefore, an event dispatch
51 dispatching is event vector based.
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| /Documentation/tee/ |
| D | op-tee.rst | 116 * Attack vector: Replace the OP-TEE OS image in the rootfs to gain control of
125 * Attack vector: Using an alternate boot mode (i.e. recovery mode), the
134 * Attack vector: Code that is executed prior to issuing the SMC call to load
144 * Attack vector: Prevent the driver from being probed, so the SMC call to
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| /Documentation/devicetree/bindings/crypto/ |
| D | xlnx,zynqmp-aes.yaml | 15 encrypt or decrypt the data with provided key and initialization vector.
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| /Documentation/arch/powerpc/ |
| D | elf_hwcaps.rst | 17 exposed in the auxiliary vector.
20 AT_HWCAP2 entry of the auxiliary vector, and testing whether the relevant
84 Vector (aka Altivec, VMX) facility is available.
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| /Documentation/virt/uml/ |
| D | user_mode_linux_howto_v2.rst | 152 supports the newer vector IO devices which are significantly faster
163 # vector UML network devices
206 | tap | vector | checksum, tso | > 8Gbit |
208 | hybrid | vector | checksum, tso, multipacket rx | > 6GBit |
210 | raw | vector | checksum, tso, multipacket rx, tx" | > 6GBit |
212 | EoGRE | vector | multipacket rx, tx | > 3Gbit |
214 | Eol2tpv3 | vector | multipacket rx, tx | > 3Gbit |
216 | bess | vector | multipacket rx, tx | > 3Gbit |
218 | fd | vector | dependent on fd type | varies |
220 | vde | vector | dep. on VDE VPN: Virt.Net Locator | varies |
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| /Documentation/arch/x86/ |
| D | intel-hfi.rst | 47 Local Vector Table of a CPU's local APIC, there exists a register for the
62 thermal entry in the Local APIC's Local Vector Table.
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| D | intel_txt.rst | 122 VMEXITs, and then disable VT and jump to the SIPI vector. This
167 - Then the kernel jumps into tboot via the vector specified in the
173 vector. This is necessary because it must re-establish the
176 transfer control back to the kernel's S3 resume vector.
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| /Documentation/virt/kvm/x86/ |
| D | msr.rst | 230 Note, since APF 'page not present' events use the same exception vector
243 Note, MSR_KVM_ASYNC_PF_INT MSR specifying the interrupt vector for 'page
359 Bits 0-7: APIC vector for delivery of 'page ready' APF events.
362 Interrupt vector for asynchnonous 'page ready' notifications delivery.
363 The vector has to be set up before asynchronous page fault mechanism
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | arm,nvic.txt | 1 * ARM Nested Vector Interrupt Controller (NVIC)
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| D | loongson,htvec.yaml | 7 title: Loongson-3 HyperTransport Interrupt Vector Controller
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| D | loongson,pch-pic.yaml | 26 u32 value of the base of parent HyperTransport vector allocated
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