Searched full:wr (Results 1 – 25 of 28) sorted by relevance
12
| /Documentation/devicetree/bindings/display/panel/ |
| D | advantech,idk-1110wr.yaml | 4 $id: http://devicetree.org/schemas/display/panel/advantech,idk-1110wr.yaml#
7 title: Advantech IDK-1110WR 10.1" WSVGA LVDS Display Panel
21 const: advantech,idk-1110wr
29 - const: advantech,idk-1110wr
57 compatible = "advantech,idk-1110wr", "panel-lvds";
|
| D | advantech,idk-2121wr.yaml | 4 $id: http://devicetree.org/schemas/display/panel/advantech,idk-2121wr.yaml#
7 title: Advantech IDK-2121WR 21.5" Full-HD dual-LVDS panel
14 The IDK-2121WR from Advantech is a Full-HD dual-LVDS panel.
28 - const: advantech,idk-2121wr
83 compatible = "advantech,idk-2121wr", "panel-lvds";
|
| D | panel-lvds.yaml | 28 - advantech,idk-1110wr
29 - advantech,idk-2121wr
|
| /Documentation/i2c/ |
| D | smbus-protocol.rst | 42 Rd/Wr (1 bit) Read/Write bit. Rd equals 1, Wr equals 0.
60 This sends a single bit to the device, at the place of the Rd/Wr bit::
62 S Addr Rd/Wr [A] P
92 S Addr Wr [A] Data [A] P
105 S Addr Wr [A] Comm [A] Sr Addr Rd [A] [Data] NA P
119 S Addr Wr [A] Comm [A] Sr Addr Rd [A] [DataLow] A [DataHigh] NA P
139 S Addr Wr [A] Comm [A] Data [A] P
153 S Addr Wr [A] Comm [A] DataLow [A] DataHigh [A] P
168 S Addr Wr [A] Comm [A] DataLow [A] DataHigh [A]
185 S Addr Wr [A] Comm [A]
[all …]
|
| D | i2c-protocol.rst | 14 Rd/Wr (1 bit) Read/Write bit. Rd equals 1, Wr equals 0.
30 S Addr Wr [A] Data [A] Data [A] ... [A] Data [A] P
50 S Addr Rd [A] [Data] NA S Addr Wr [A] Data [A] P
70 In a combined transaction, no 'S Addr Wr/Rd [A]' is generated at some
87 This toggles the Rd/Wr flag. That is, if you want to do a write, but
88 need to emit an Rd instead of a Wr, or vice versa, you set this
|
| /Documentation/translations/it_IT/i2c/ |
| D | i2c-protocol.rst | 14 Rd/Wr (1 bit) Bit di lettura/scrittura. Rd vale 1, Wr vale 0.
30 S Addr Wr [A] Dati [A] Dati [A] ... [A] Dati [A] P
50 S Addr Rd [A] [Dati] NA S Addr Wr [A] Dati [A] P
72 "S Addr Wr/Rd [A]".
89 Questo inverte il flag Rd/Wr. Cioè, se si vuole scrivere, ma si ha bisogno
90 di emettere una Rd invece di una Wr, o viceversa, si può impostare questo
|
| /Documentation/devicetree/bindings/display/samsung/ |
| D | samsung,fimd.yaml | 52 | wr-setup+1 | | wr-hold+1 |
55 | wr-active+1|
67 wr-active:
73 wr-hold:
80 wr-setup:
|
| D | samsung,exynos7-decon.yaml | 49 wr-active:
55 wr-hold:
62 wr-setup:
|
| /Documentation/devicetree/bindings/memory-controllers/ |
| D | mvebu-devbus.txt | 85 - devbus,ale-wr-ps: Defines the time delay from the ALE[0] negation cycle
89 - devbus,wr-low-ps: Defines the time during which DEV_WEn is active.
95 - devbus,wr-high-ps: Defines the time during which DEV_WEn is kept
98 <wr-high-ps> - <tick> ps.
150 devbus,wr-high-ps = <60000>;
151 devbus,wr-low-ps = <60000>;
152 devbus,ale-wr-ps = <60000>;
|
| D | ti,gpmc-child.yaml | 37 gpmc,cs-wr-off-ns:
50 gpmc,adv-wr-off-ns:
62 gpmc,adv-aad-mux-wr-off-ns:
106 gpmc,wr-cycle-ns:
161 gpmc,wr-access-ns:
170 gpmc,wr-data-mux-bus-ns:
|
| D | atmel,ebi.txt | 85 - atmel,smc-ncs-wr-setup-ns
89 - atmel,smc-ncs-wr-pulse-ns
125 atmel,smc-ncs-wr-setup-ns = <0>;
129 atmel,smc-ncs-wr-pulse-ns = <84>;
|
| /Documentation/devicetree/bindings/mtd/ |
| D | lpc32xx-mlc.txt | 38 nxp,wr-high = <40000000>;
39 nxp,wr-low = <83333333>;
|
| /Documentation/spi/ |
| D | spidev.rst | 122 return (RD) or assign (WR) the SPI transfer mode. Use the constants
131 which will return (RD) or assign (WR) the full SPI transfer mode,
136 which will return (RD) or assign (WR) the bit justification used to
144 a byte which will return (RD) or assign (WR) the number of bits in
149 u32 which will return (RD) or assign (WR) the maximum SPI transfer
|
| /Documentation/devicetree/bindings/mips/cavium/ |
| D | bootbus.txt | 42 - cavium,t-wr-hld: A cell specifying the WR_HLD timing (in nS).
93 cavium,t-wr-hld = <45>;
113 cavium,t-wr-hld = <70>;
|
| /Documentation/devicetree/bindings/dma/ |
| D | intel,ldma.yaml | 76 intel,dma-dburst-wr:
115 intel,dma-dburst-wr;
|
| /Documentation/translations/zh_CN/PCI/ |
| D | pci.rst | 221 这将启用 ``Mem-Wr-Inval`` 的 ``PCI_COMMAND`` 位，也确保缓存行大小寄存器被正确设置。检
223 另外，如果 ``Mem-Wr-Inval`` 是好的，但不是必须的，可以调用 ``pci_try_set_mwi()`` ，让
224 系统尽最大努力来启用 ``Mem-Wr-Inval`` 。
|
| /Documentation/virt/kvm/x86/ |
| D | errata.rst | 55 MSRs, i.e. {RD,WR}MSR in the guest will behave as expected, but KVM does not
|
| /Documentation/devicetree/bindings/soc/imx/ |
| D | fsl,imx8mp-media-blk-ctrl.yaml | 79 - const: lcdif-wr
|
| /Documentation/devicetree/bindings/iio/resolver/ |
| D | adi,ad2s1210.yaml | 45 logic low and the WR/FSYNC line on the AD2S1210 should be connected to the
|
| /Documentation/devicetree/bindings/edac/ |
| D | socfpga-eccmgr.txt | 193 nand-wr-ecc@ff8c2800 {
356 nand-wr-ecc@ff8c8800 {
|
| /Documentation/mm/ |
| D | page_table_check.rst | 27 userfaultfd is the only user of such to sanity check wr-protect bit against
|
| /Documentation/devicetree/bindings/pinctrl/ |
| D | lantiq,pinctrl-xway.txt | 95 nand_d6, nand_d7, nand_d1, nand wr, nand wp, nand se, spi_di, spi_do,
|
| /Documentation/PCI/ |
| D | pci.rst | 227 call pci_set_mwi(). This enables the PCI_COMMAND bit for Mem-Wr-Inval
231 if Mem-Wr-Inval would be nice to have but is not required, call
233 Mem-Wr-Inval.
|
| /Documentation/driver-api/surface_aggregator/clients/ |
| D | cdev.rst | 77 - ``WR``
|
| /Documentation/arch/sparc/oradax/ |
| D | oracle-dax.rst | 359 __asm__ __volatile__("wr %%g0, 1000, %%asr28\n" ::); /* 1000 ns */
430 __asm__ __volatile__("wr %%g0, 1000, %%asr28\n" ::); /* 1000 ns */
|
12