Searched full:x3 (Results 1 – 25 of 138) sorted by relevance
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| /Documentation/devicetree/bindings/soc/ti/ |
| D | ti,j721e-system-controller.yaml | 95 <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
96 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
97 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
98 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
99 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
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| D | ti,am654-serdes-ctrl.yaml | 41 mux-reg-masks = <0x0 0x3>; /* lane select */
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| /Documentation/devicetree/bindings/iio/light/ |
| D | ti,opt4001.yaml | 15 Picostar is a 4 pinned SMT and sot-5x3 is a 8 pinned SOT.
22 - ti,opt4001-sot-5x3
42 const: ti,opt4001-sot-5x3
61 compatible = "ti,opt4001-sot-5x3";
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| /Documentation/devicetree/bindings/dma/stm32/ |
| D | st,stm32-mdma.yaml | 20 0x3: Very high
25 0x3: Source address pointer is decremented after each data transfer
29 0x3: Destination address pointer is decremented after each data transfer
34 0x3: double-word (64bit)
39 0x3: double-word (64bit)
46 0x3: Each MDMA request triggers a linked list transfer
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| D | st,stm32-dma.yaml | 32 0x3: very high
38 0x3: full FIFO
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | fsl,imx8ulp-pinctrl.yaml | 77 <0x0138 0x08F0 0x4 0x3 0x3>,
78 <0x013C 0x08EC 0x4 0x3 0x3>;
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| /Documentation/devicetree/bindings/regulator/ |
| D | qcom-labibb-regulator.yaml | 89 interrupts = <0x3 0xde 0x1 IRQ_TYPE_EDGE_RISING>,
90 <0x3 0xde 0x0 IRQ_TYPE_LEVEL_LOW>;
95 interrupts = <0x3 0xdc 0x2 IRQ_TYPE_EDGE_RISING>,
96 <0x3 0xdc 0x0 IRQ_TYPE_LEVEL_LOW>;
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| D | mps,mpq2286.yaml | 47 reg = <0x3>;
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| /Documentation/input/devices/ |
| D | alps.rst | 95 byte 1: X7 X6 X5 X4 X3 X2 X1 X0
110 byte 1: 0 x6 x5 x4 x3 x2 x1 x0
122 byte 1: 0 x6 x5 x4 x3 x2 x1 x0
140 byte 1: 0 x6 x5 x4 x3 x2 x1 x0
143 byte 4: X7 X6 X5 X4 X3 X2 X1 X0
167 byte 4: 0 mt x3 x2 y3 y2 y1 y0
180 byte 1: 0 x8 x7 x6 x5 x4 x3 x2
193 byte 1: 0 x6 x5 x4 x3 x2 x1 x0
210 byte 3: 0 1 x3 x2 y3 y2 y1 y0
220 byte 0: 0 1 x7 x6 x5 x4 x3 x2
[all …]
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| /Documentation/devicetree/bindings/pci/ |
| D | rockchip-dw-pcie.yaml | 89 reg = <0x3 0xc0800000 0x0 0x390000>,
91 <0x3 0x80000000 0x0 0x100000>;
114 ranges = <0x81000000 0x0 0x80800000 0x3 0x80800000 0x0 0x100000>,
115 <0x83000000 0x0 0x80900000 0x3 0x80900000 0x0 0x3f700000>;
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| D | 83xx-512x-pci.txt | 17 0x7000 0x0 0x0 0x3 &ipic 18 0x8
23 0x7800 0x0 0x0 0x3 &ipic 17 0x8
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| D | starfive,jh7110-pcie.yaml | 97 <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
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| /Documentation/devicetree/bindings/mux/ |
| D | reg-mux.yaml | 110 <0x3 0x30>, /* 0: reg 0x3, bits 5:4 */
111 <0x3 0x40>; /* 1: reg 0x3, bit 6 */
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| /Documentation/devicetree/bindings/goldfish/ |
| D | battery.txt | 16 interrupts = <0x3>;
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-stp-xway.yaml | 58 maximum: 0x3
95 lantiq,dsl = <0x3>;
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| /Documentation/arch/powerpc/ |
| D | ptrace.rst | 64 #define PPC_BREAKPOINT_MODE_MASK 0x3
67 #define PPC_BREAKPOINT_CONDITION_MODE 0x3
72 #define PPC_BREAKPOINT_CONDITION_AND_OR 0x3
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| /Documentation/devicetree/bindings/cache/ |
| D | marvell,tauros2-cache.txt | 16 marvell,tauros2-cache-features = <0x3>;
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| /Documentation/ABI/testing/ |
| D | debugfs-iio-backend | 18 echo 0x50 0x3 > direct_reg_access
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| D | sysfs-bus-iio-mpu6050 | 8 is a 3x3 unitary matrix. A typical mounting matrix would look like
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| D | sysfs-class-extcon | 90 {0x3, 0x5, 0xC, 0x0}, then the output is::
93 0x3
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| /Documentation/devicetree/bindings/sound/ |
| D | cs35l33.txt | 80 The reference voltage starts at 3000mV with a value of 0x3 and is increased
114 cirrus,mem-depth = <0x3>;
115 cirrus,release-rate = <0x3>;
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| /Documentation/gpu/amdgpu/ |
| D | debugging.rst | 32 PERMISSION_FAULTS: 0x3
70 an invalid page (PERMISSION_FAULTS = 0x3) at GPU virtual address
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| /Documentation/devicetree/bindings/ata/ |
| D | baikal,bt1-ahci.yaml | 46 maximum: 0x3
99 ports-implemented = <0x3>;
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| /Documentation/devicetree/bindings/net/dsa/ |
| D | qca,ar9331.yaml | 117 reg = <0x3>;
151 reg = <0x3>;
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| /Documentation/devicetree/bindings/leds/ |
| D | leds-lp50xx.yaml | 137 reg = <0x3>, <0x4>, <0x5>;
142 reg = <0x3>;
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