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/Documentation/arch/arm/
Dmemory.rst25 For SA11xx and Xscale, this is used to
38 fffe0000 fffeffff XScale cache flush area. This is used
39 in proc-xscale.S to flush the whole data
40 cache. (XScale does not have TCM.)
Dmarvell.rst368 * This line of SoCs originates from the XScale family developed by
373 * Due to their XScale origin, these SoCs have virtually nothing in
422 * This line of SoCs originates from the XScale family developed by
426 * Due to their XScale origin, these SoCs have virtually nothing in
471 The XScale cores were designed by Intel, and shipped by Marvell in the older
473 and that evolved into Sheeva. The XScale and Feroceon cores were phased out
477 XScale 1
480 XScale 2
483 XScale 3
/Documentation/devicetree/bindings/i2c/
Di2c-iop3xx.txt1 i2c Controller on XScale platforms such as IOP3xx and IXP4xx
/Documentation/devicetree/bindings/timer/
Dintel,ixp4xx-timer.yaml8 title: Intel IXP4xx XScale Networking Processors Timers
/Documentation/devicetree/bindings/interrupt-controller/
Dintel,ixp4xx-interrupt.yaml8 title: Intel IXP4xx XScale Networking Processors Interrupt Controller
/Documentation/devicetree/bindings/net/
Dintel,ixp46x-ptp-timer.yaml16 timer. It exists in the Intel IXP45x and IXP46x XScale SoCs.
/Documentation/devicetree/bindings/misc/
Dintel,ixp4xx-ahb-queue-manager.yaml16 the XScale processor and the NPEs (Network Processing Units) in the
/Documentation/devicetree/bindings/gpio/
Dintel,ixp4xx-gpio.yaml7 title: Intel IXP4xx XScale Networking Processors GPIO Controller
/Documentation/devicetree/bindings/serial/
D8250.yaml62 - const: intel,xscale-uart
115 - const: intel,xscale-uart
/Documentation/crypto/
Dasync-tx-api.rst44 present in the Intel(R) Xscale series of I/O processors. It also built
/Documentation/scsi/
DChangeLog.megaraid_sas205 a). reset the controller chips -- Xscale and Gen2 which
602 xscale controllers.