Searched +full:a +full:- +full:display (Results 1 – 25 of 536) sorted by relevance
12345678910>>...22
| /Documentation/devicetree/bindings/auxdisplay/ |
| D | modtronix,lcd2s.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Modtronix engineering LCD2S Character LCD Display
10 - Lars Poeschel <poeschel@lemonage.de>
13 The LCD2S is a Character LCD Display manufactured by Modtronix Engineering.
14 The display supports a serial I2C and SPI interface. The driver currently
24 I2C bus address of the display.
26 display-height-chars:
27 description: Height of the display, in character cells.
[all …]
|
| /Documentation/gpu/amdgpu/display/ |
| D | index.rst | 1 .. _amdgpu-display-core:
4 drm/amd/display - Display Core (DC)
7 AMD display engine is partially shared with other operating systems; for this
8 reason, our Display Core Driver is divided into two pieces:
10 #. **Display Core (DC)** contains the OS-agnostic components. Things like
12 #. **Display Manager (DM)** contains the OS-dependent components. Hooks to the
14 display/amdgpu_dm/ folder.
16 ------------------
18 ------------------
20 Maintaining the same code base across multiple OSes requires a lot of
[all …]
|
| D | dcn-overview.rst | 2 Display Core Next (DCN)
5 To equip our readers with the basic knowledge of how AMD Display Core Next
7 you can see a picture that provides a DCN overview, keep in mind that this is a
10 .. kernel-figure:: dc_pipeline_overview.svg
15 * **Display Controller Hub (DCHUB)**: This is the gateway between the Scalable
19 * **Display Pipe and Plane (DPP)**: This block provides pre-blend pixel
24 multiple planes, using global or per-pixel alpha.
27 the display.
32 * **Display Output (DIO)**: Codify the output to the display connected to our
35 * **Display Writeback (DWB)**: It provides the ability to write the output of
[all …]
|
| D | mpo-overview.rst | 6 'Documentation/gpu/amdgpu/display/dcn-overview.rst'.
10 fixed-function hardware in the display controller rather than using graphics or
12 the graphics/compute pipelines can be put into low-power states. In summary,
15 * Decreased GPU and CPU workload - no composition shaders needed, no extra
17 * Plane independent page flips - No need to be tied to global compositor
18 page-flip present rate, reduced latency, independent timing.
20 .. note:: Keep in mind that MPO is all about power-saving; if you want to learn
21 more about power-save in the display context, check the link:
22 `Power <https://gitlab.freedesktop.org/pq/color-and-hdr/-/blob/main/doc/power.rst>`__.
25 model only uses a single userspace IOCTL for configuring the display hardware
[all …]
|
| D | display-manager.rst | 2 AMDgpu Display Manager
8 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
11 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
17 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
20 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
26 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
29 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c
32 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
38 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
41 .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
[all …]
|
| /Documentation/devicetree/bindings/display/panel/ |
| D | panel-common.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common Properties for Display Panels
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
15 display panels. It doesn't constitute a device tree binding specification by
24 width-mm:
29 height-mm:
[all …]
|
| D | panel-simple.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-simple.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Sam Ravnborg <sam@ravnborg.org>
14 This binding file is a collection of the simple (dumb) panels that
15 requires only a single power-supply.
16 There are optionally a backlight and an enable GPIO.
17 The panel may use an OF graph binding for the association to the display,
[all …]
|
| /Documentation/devicetree/bindings/display/ |
| D | simple-framebuffer.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/simple-framebuffer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hans de Goede <hdegoede@redhat.com>
13 A simple frame-buffer describes a frame-buffer setup by firmware or
14 the bootloader, with the assumption that the display hardware has
19 sub-nodes of the chosen node (*). Simplefb nodes must be named
22 If the devicetree contains nodes for the display hardware used by a
23 simplefb, then the simplefb node must contain a property called
[all …]
|
| D | cirrus,clps711x-fb.txt | 4 - compatible: Shall contain "cirrus,ep7209-fb".
5 - reg : Physical base address and length of the controller's registers +
7 - clocks : phandle + clock specifier pair of the FB reference clock.
8 - display : phandle to a display node as described in
9 Documentation/devicetree/bindings/display/panel/display-timing.txt.
10 Additionally, the display node has to define properties:
11 - bits-per-pixel: Bits per pixel.
12 - ac-prescale : LCD AC bias frequency. This frequency is the required
13 AC bias frequency for a given manufacturer's LCD plate.
14 - cmap-invert : Invert the color levels (Optional).
[all …]
|
| D | xylon,logicvc-display.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Xylon LogiCVC display controller
11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
14 The Xylon LogiCVC is a display controller that supports multiple layers.
16 with Xilinx Zynq-7000 SoCs and Xilinx FPGAs.
18 Because the controller is intended for use in a FPGA, most of the
20 synthesis time. As a result, many of the device-tree bindings are meant to
[all …]
|
| D | atmel,lcdc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/atmel,lcdc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Dharma Balasubiramani <dharma.b@microchip.com>
14 The LCDC works with a framebuffer, which is a section of memory that contains
15 a complete frame of data representing pixel values for the display. The LCDC
22 - atmel,at91sam9261-lcdc
23 - atmel,at91sam9263-lcdc
[all …]
|
| D | atmel,lcdc-display.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/atmel,lcdc-display.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip's LCDC Display
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Dharma Balasubiramani <dharma.b@microchip.com>
15 from an external display buffer to a TFT LCD panel. The LCDC has one display
17 interface and a look-up table to allow palletized display configurations. The
18 LCDC is programmable on a per layer basis, and supports different LCD
[all …]
|
| D | allwinner,sun4i-a10-display-engine.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A10 Display Engine Pipeline
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 The display engine pipeline (and its entry point, since it can be
18 The Allwinner A10 Display pipeline is composed of several components
22 display pipeline, when there are multiple components of the same
[all …]
|
| D | repaper.txt | 1 Pervasive Displays RePaper branded e-ink displays
4 - compatible: "pervasive,e1144cs021" for 1.44" display
5 "pervasive,e1190cs021" for 1.9" display
6 "pervasive,e2200cs021" for 2.0" display
7 "pervasive,e2271cs021" for 2.7" display
9 - panel-on-gpios: Timing controller power control
10 - discharge-gpios: Discharge control
11 - reset-gpios: RESET pin
12 - busy-gpios: BUSY pin
15 - border-gpios: Border control
[all …]
|
| /Documentation/userspace-api/media/v4l/ |
| D | ext-ctrls-colorimetry.rst | 1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _colorimetry-controls:
15 -----------------------
17 .. _colorimetry-control-id:
22 return a description of this control class.
32 .. flat-table:: struct v4l2_ctrl_hdr10_cll_info
33 :header-rows: 0
34 :stub-columns: 0
37 * - __u16
38 - ``max_content_light_level``
[all …]
|
| /Documentation/gpu/ |
| D | tegra.rst | 2 drm/tegra NVIDIA Tegra GPU and display driver
5 NVIDIA Tegra SoCs support a set of display, graphics and video functions via
6 the host1x controller. host1x supplies command streams, gathered from a push
11 supports the built-in GPU, comprised of the gr2d and gr3d engines. Starting
18 - A host1x driver that provides infrastructure and access to the host1x
21 - A KMS driver that supports the display controllers as well as a number of
24 - A set of custom userspace IOCTLs that can be used to submit jobs to the
30 The various host1x clients need to be bound together into a logical device in
32 this is implemented in the host1x driver. When a driver is registered with the
33 infrastructure it provides a list of compatible strings specifying the devices
[all …]
|
| D | komeda-kms.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 drm/komeda Arm display driver
7 The drm/komeda driver supports the Arm display processor D71 and later products,
8 this document gives a brief overview of driver design: how it works and why
11 Overview of D71 like display IPs
14 From D71, Arm display IP begins to adopt a flexible and modularized
15 architecture. A display pipeline is made up of multiple individual and
17 specific capabilities that can give the flowed pipeline pixel data a
23 -----
30 ------
[all …]
|
| /Documentation/devicetree/bindings/display/msm/ |
| D | qcom,mdss.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Mobile Display SubSystem (MDSS)
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11 - Rob Clark <robdclark@gmail.com>
14 This is the bindings documentation for the Mobile Display Subsystem(MDSS) that
15 encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc.
19 pattern: "^display-subsystem@[0-9a-f]+$"
[all …]
|
| /Documentation/devicetree/bindings/display/rockchip/ |
| D | rockchip-drm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only)
3 ---
4 $id: http://devicetree.org/schemas/display/rockchip/rockchip-drm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sandy Huang <hjc@rock-chips.com>
11 - Heiko Stuebner <heiko@sntech.de>
14 The Rockchip DRM master device is a virtual device needed to list all
15 vop devices or other display interface nodes that comprise the
20 const: rockchip,display-subsystem
23 $ref: /schemas/types.yaml#/definitions/phandle-array
[all …]
|
| /Documentation/devicetree/bindings/display/imx/ |
| D | ldb.txt | 1 Device-Tree bindings for LVDS Display Bridge (ldb)
3 LVDS Display Bridge
6 The LVDS Display Bridge device tree node contains up to two lvds-channel
10 - #address-cells : should be <1>
11 - #size-cells : should be <0>
12 - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb".
14 multiplexer in the front to select any of the four IPU display
16 - gpr : should be <&gpr> on i.MX53 and i.MX6q.
17 The phandle points to the iomuxc-gpr region containing the LVDS
19 - clocks, clock-names : phandles to the LDB divider and selector clocks and to
[all …]
|
| D | nxp,imx8mq-dcss.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: iMX8MQ Display Controller Subsystem (DCSS)
11 - Laurentiu Palcu <laurentiu.palcu@nxp.com>
15 The DCSS (display controller sub system) is used to source up to three
16 display buffers, compose them, and drive a display using HDMI 2.0a(with HDCP
17 2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10
18 image processing capabilities are included to provide a solution capable of
[all …]
|
| /Documentation/devicetree/bindings/display/tegra/ |
| D | nvidia,tegra186-dc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra186-dc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 (and later) Display Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^display@[0-9a-f]+$"
19 - nvidia,tegra186-dc
20 - nvidia,tegra194-dc
[all …]
|
| /Documentation/devicetree/bindings/mfd/ |
| D | xylon,logicvc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Xylon LogiCVC multi-function device
11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
14 The LogiCVC is a display controller that also contains a GPIO controller.
15 As a result, a multi-function device is exposed as parent of the display
21 - enum:
22 - xylon,logicvc-3.02.a
23 - const: syscon
[all …]
|
| /Documentation/devicetree/bindings/display/sprd/ |
| D | sprd,display-subsystem.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/sprd/sprd,display-subsystem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kevin Tang <kevin.tang@unisoc.com>
13 The Unisoc DRM master device is a virtual device needed to list all
14 DPU devices or other display interface nodes that comprise the
17 Unisoc's display pipeline have several components as below description,
18 multi display controllers and corresponding physical interfaces.
19 For different display scenarios, dpu0 and dpu1 maybe binding to different
[all …]
|
| /Documentation/devicetree/bindings/display/atmel/ |
| D | atmel,hlcdc-display-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/atmel/atmel,hlcdc-display-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nicolas Ferre <nicolas.ferre@microchip.com>
11 - Alexandre Belloni <alexandre.belloni@bootlin.com>
12 - Claudiu Beznea <claudiu.beznea@tuxon.dev>
16 data from an external display buffer to a TFT LCD panel. The LCDC has one
17 display input buffer per layer that fetches pixels through the single bus
18 host interface and a look-up table to allow palletized display
[all …]
|
12345678910>>...22