Searched +full:a +full:- +full:gpio (Results 1 – 25 of 974) sorted by relevance
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| /Documentation/driver-api/gpio/ |
| D | drivers-on-gpio.rst | 2 Subsystem drivers using GPIO
5 Note that standard kernel drivers exist for common GPIO tasks and will provide
6 the right in-kernel and userspace APIs/ABIs for the job, and that these
10 - leds-gpio: drivers/leds/leds-gpio.c will handle LEDs connected to GPIO
13 - ledtrig-gpio: drivers/leds/trigger/ledtrig-gpio.c will provide a LED trigger,
14 i.e. a LED will turn on/off in response to a GPIO line going high or low
15 (and that LED may in turn use the leds-gpio as per above).
17 - gpio-keys: drivers/input/keyboard/gpio_keys.c is used when your GPIO line
18 can generate interrupts in response to a key press. Also supports debounce.
20 - gpio-keys-polled: drivers/input/keyboard/gpio_keys_polled.c is used when your
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| D | driver.rst | 2 GPIO Driver Interface
5 This document serves as a guide for writers of GPIO chip drivers.
7 Each GPIO controller driver needs to include the following header, which defines
8 the structures used to define a GPIO driver::
10 #include <linux/gpio/driver.h>
16 A GPIO chip handles one or more GPIO lines. To be considered a GPIO chip, the
18 line is not general purpose, it is not GPIO and should not be handled by a
19 GPIO chip. The use case is the indicative: certain lines in a system may be
20 called GPIO but serve a very particular purpose thus not meeting the criteria
21 of a general purpose I/O. On the other hand a LED driver line may be used as a
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| D | intro.rst | 6 GPIO Interfaces
10 GPIOs in drivers, and how to write a driver for a device that provides GPIOs
14 What is a GPIO?
17 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
19 to Linux developers working with embedded and custom hardware. Each GPIO
20 represents a bit connected to a particular pin, or "ball" on Ball Grid Array
25 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
26 non-dedicated pin can be configured as a GPIO; and most chips have at least
29 often have a few such pins to help with pin scarcity on SOCs; and there are
30 also "GPIO Expander" chips that connect using the I2C or SPI serial buses.
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio.txt | 1 Specifying GPIO information for devices
5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
14 GPIO properties can contain one or more GPIO phandles, but only in exceptional
16 distinct functions, reference each of them under its own property, giving it a
18 several GPIOs serve the same function (e.g. a parallel data line).
23 The following example could be used to describe GPIO pins used as device enable
24 and bit-banged data signals:
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| D | nvidia,tegra186-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra186-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra GPIO Controller (Tegra186 and later)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 Tegra186 contains two GPIO controllers; a main controller and an "AON"
20 The Tegra186 GPIO controller allows software to set the IO direction of,
21 and read/write the value of, numerous GPIO signals. Routing of GPIO signals
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| D | gpio-mmio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-mmio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic MMIO GPIO
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Bartosz Golaszewski <brgl@bgdev.pl>
14 Some simple GPIO controllers may consist of a single data register or a pair
15 of set/clear-bit registers. Such controllers are common for glue logic in
16 FPGAs or ASICs. Commonly, these controllers are accessed over memory-mapped
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| D | snps,dw-apb-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/snps,dw-apb-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare APB GPIO controller
10 Synopsys DesignWare GPIO controllers have a configurable number of ports,
12 GPIO-controller properties as described in this bindings file.
15 - Hoan Tran <hoan@os.amperecomputing.com>
16 - Serge Semin <fancer.lancer@gmail.com>
20 pattern: "^gpio@[0-9a-f]+$"
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| D | ibm,ppc4xx-gpio.txt | 1 * IBM/AMCC/APM GPIO Controller for PowerPC 4XX series and compatible SoCs
3 All GPIOs are pin-shared with other functions. DCRs control whether a
4 particular pin that has GPIO capabilities acts as a GPIO or is used for
5 another purpose. GPIO outputs are separately programmable to emulate
6 an open-drain driver.
9 - compatible: must be "ibm,ppc4xx-gpio"
10 - reg: address and length of the register set for the device
11 - #gpio-cells: must be set to 2. The first cell is the pin number
12 and the second cell is used to specify the gpio polarity:
15 - gpio-controller: marks the device node as a gpio controller.
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| D | gpio-xgene.txt | 1 APM X-Gene SoC GPIO controller bindings
3 This is a gpio controller that is part of the flash controller.
4 This gpio controller controls a total of 48 gpios.
7 - compatible: "apm,xgene-gpio" for X-Gene GPIO controller
8 - reg: Physical base address and size of the controller's registers
9 - #gpio-cells: Should be two.
10 - first cell is the pin number
11 - second cell is used to specify the gpio polarity:
14 - gpio-controller: Marks the device node as a GPIO controller.
18 compatible = "apm,xgene-gpio";
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| D | xylon,logicvc-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/gpio/xylon,logicvc-gpio.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Xylon LogiCVC GPIO controller
11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
14 The LogiCVC GPIO describes the GPIO block included in the LogiCVC display
15 controller. These are meant to be used for controlling display-related
20 - GPIO[4:0] (display control) mapped to index 0-4
21 - EN_BLIGHT (power control) mapped to index 5
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| D | gpio-twl4030.txt | 1 twl4030 GPIO controller bindings
4 - compatible:
5 - "ti,twl4030-gpio" for twl4030 GPIO controller
6 - #gpio-cells : Should be two.
7 - first cell is the pin number
8 - second cell is used to specify optional parameters (unused)
9 - gpio-controller : Marks the device node as a GPIO controller.
10 - #interrupt-cells : Should be 2.
11 - interrupt-controller: Mark the device node as an interrupt controller
12 The first cell is the GPIO number.
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| D | xlnx,gpio-xilinx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/xlnx,gpio-xilinx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx AXI GPIO controller
10 - Neeli Srinivas <srinivas.neeli@amd.com>
13 The AXI GPIO design provides a general purpose input/output interface
14 to an AXI4-Lite interface. The AXI GPIO can be configured as either
15 a single or a dual-channel device. The width of each channel is
17 generate an interrupt when a transition on any of their inputs occurs.
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| /Documentation/admin-guide/gpio/ |
| D | gpio-aggregator.rst | 1 .. SPDX-License-Identifier: GPL-2.0-only
3 GPIO Aggregator
6 The GPIO Aggregator provides a mechanism to aggregate GPIOs, and expose them as
7 a new gpio_chip. This supports the following use cases.
11 -----------------------------
13 GPIO controllers are exported to userspace using /dev/gpiochip* character
15 system permissions, on an all-or-nothing basis: either a GPIO controller is
16 accessible for a user, or it is not.
18 The GPIO Aggregator provides access control for a set of one or more GPIOs, by
19 aggregating them into a new gpio_chip, which can be assigned to a group or user
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| D | gpio-virtuser.rst | 1 .. SPDX-License-Identifier: GPL-2.0-only
3 Virtual GPIO Consumer
6 The virtual GPIO Consumer module allows users to instantiate virtual devices
8 consumer devices can be instantiated from device-tree or over configfs.
10 A virtual consumer uses the driver-facing GPIO APIs and allows to cover it with
11 automated tests driven by user-space. The GPIOs are requested using
14 Creating GPIO consumers
15 -----------------------
17 The gpio-consumer module registers a configfs subsystem called
18 ``'gpio-virtuser'``. For details of the configfs filesystem, please refer to
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| D | gpio-sim.rst | 1 .. SPDX-License-Identifier: GPL-2.0-or-later
3 Configfs GPIO Simulator
6 The configfs GPIO Simulator (gpio-sim) provides a way to create simulated GPIO
8 using the standard GPIO character device interface as well as manipulated
12 ------------------------
14 The gpio-sim module registers a configfs subsystem called ``'gpio-sim'``. For
17 The user can create a hierarchy of configfs groups and items as well as modify
21 **Group:** ``/config/gpio-sim``
23 This is the top directory of the gpio-sim configfs tree.
25 **Group:** ``/config/gpio-sim/gpio-device``
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | brcm,bcm2835-gpio.txt | 1 Broadcom BCM2835 GPIO (and pinmux) controller
3 The BCM2835 GPIO module is a combined GPIO controller, (GPIO) interrupt
7 - compatible: "brcm,bcm2835-gpio"
8 - compatible: should be one of:
9 "brcm,bcm2835-gpio" - BCM2835 compatible pinctrl
10 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
11 "brcm,bcm2711-gpio" - BCM2711 compatible pinctrl
12 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
13 - reg: Should contain the physical address of the GPIO module's registers.
14 - gpio-controller: Marks the device node as a GPIO controller.
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| D | pinctrl-vt8500.txt | 1 VIA VT8500 and Wondermedia WM8xxx-series pinmux/gpio controller
3 These SoCs contain a combined Pinmux/GPIO module. Each pin may operate as
4 either a GPIO in, GPIO out or as an alternate function (I2C, SPI etc).
7 - compatible: "via,vt8500-pinctrl", "wm,wm8505-pinctrl", "wm,wm8650-pinctrl",
8 "wm8750-pinctrl" or "wm,wm8850-pinctrl"
9 - reg: Should contain the physical address of the module's registers.
10 - interrupt-controller: Marks the device node as an interrupt controller.
11 - #interrupt-cells: Should be two.
12 - gpio-controller: Marks the device node as a GPIO controller.
13 - #gpio-cells : Should be two. The first cell is the pin number and the
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| D | ingenic,pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Please refer to pinctrl-bindings.txt in this directory for details of the
14 For the Ingenic SoCs, pin control is tightly bound with GPIO ports. All pins
16 GPIO port configuration registers and it is typical to refer to pins using the
17 naming scheme "PxN" where x is a character identifying the GPIO port with
19 pin within that GPIO port. For example PA0 is the first pin in GPIO port A,
20 and PB31 is the last pin in GPIO port B. The JZ4730, the JZ4740, the JZ4725B,
21 the X1000 and the X1830 contains 4 GPIO ports, PA to PD, for a total of 128
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| D | brcm,nsp-gpio.txt | 1 Broadcom Northstar plus (NSP) GPIO/PINCONF Controller
4 - compatible:
5 Must be "brcm,nsp-gpio-a"
7 - reg:
9 GPIO base, IO control registers
11 - #gpio-cells:
12 Must be two. The first cell is the GPIO pin number (within the
16 - gpio-controller:
17 Specifies that the node is a GPIO controller
19 - ngpios:
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| /Documentation/devicetree/bindings/power/reset/ |
| D | gpio-restart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/gpio-restart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO controlled reset
10 - Sebastian Reichel <sre@kernel.org>
13 Drive a GPIO line that can be used to restart the system from a restart handler.
16 request the given gpio line and install a restart handler. If the optional properties
17 'open-source' is not found, the GPIO line will be driven in the inactive state. Otherwise its
20 When the system is restarted, the restart handler will be invoked in priority order. The GPIO
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| /Documentation/userspace-api/gpio/ |
| D | sysfs.rst | 1 GPIO Sysfs Interface for Userspace
6 been moved to Documentation/ABI/obsolete/sysfs-gpio.
16 ----------------------
18 configure a sysfs user interface to GPIOs. This is different from the
19 debugfs interface, since it provides control over GPIO direction and
20 value instead of just showing a gpio state summary. Plus, it could be
24 know for example that GPIO #23 controls the write protect line used to
26 may need to temporarily remove that protection, first importing a GPIO,
27 then changing its output state, then updating the code before re-enabling
28 the write protection. In normal use, GPIO #23 would never be touched,
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| D | chardev_v1.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 GPIO Character Device Userspace API (v1)
12 in the future. The v2 API is a functional superset of the v1 API so any
13 v1 call can be directly translated to a v2 equivalent.
20 The API is based around three major objects, the :ref:`gpio-v1-chip`, the
21 :ref:`gpio-v1-line-handle`, and the :ref:`gpio-v1-line-event`.
24 monitor a line for edge events, not the edge events themselves.
26 .. _gpio-v1-chip:
31 The Chip represents a single GPIO chip and is exposed to userspace using device
34 Each chip supports a number of GPIO lines,
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| /Documentation/devicetree/bindings/sound/ |
| D | cirrus,cs35l45.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ricardo Rivera-Matos <rriveram@opensource.cirrus.com>
11 - Richard Fitzgerald <rf@opensource.cirrus.com>
14 CS35L45 is a Boosted Mono Class D Amplifier with DSP
18 - $ref: dai-common.yaml#
23 - cirrus,cs35l45
31 '#sound-dai-cells':
34 reset-gpios:
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| /Documentation/devicetree/bindings/soc/fsl/cpm_qe/ |
| D | gpio.txt | 1 Every GPIO controller node must have #gpio-cells property defined,
2 this information will be used to translate gpio-specifiers.
5 Ports A, C and D are 16bit ports and Ports B and E are 32bit ports.
7 On CPM2 devices, all ports are 32bit ports and use a common register layout.
10 - compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
11 "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
12 "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
13 - #gpio-cells : Should be two. The first cell is the pin number and the
15 - gpio-controller : Marks the port as GPIO controller.
17 - fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
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| /Documentation/devicetree/bindings/mfd/ |
| D | kontron,sl28cpld.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Walle <michael@walle.cc>
14 watchdog, fan monitoring, PWM controller, interrupt controller and a
15 GPIO controller.
26 "#address-cells":
29 "#size-cells":
32 "#interrupt-cells":
38 interrupt-controller: true
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