Searched +full:access +full:- +full:controllers (Results 1 – 25 of 146) sorted by relevance
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| /Documentation/devicetree/bindings/access-controllers/ |
| D | access-controllers.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/access-controllers/access-controllers.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic Domain Access Controllers
10 - Oleksii Moisieiev <oleksii_moisieiev@epam.com>
13 Common access controllers properties
15 Access controllers are in charge of stating which of the hardware blocks under
18 or a group of hardware blocks. An access controller's domain is the set of
19 resources covered by the access controller.
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| /Documentation/devicetree/bindings/bus/ |
| D | st,stm32-etzpc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/st,stm32-etzpc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 devices with programmable-security attributes (securable resources).
14 - Gatien Chevallier <gatien.chevallier@foss.st.com>
20 const: st,stm32-etzpc
22 - compatible
27 - const: st,stm32-etzpc
28 - const: simple-bus
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| D | st,stm32mp25-rifsc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/st,stm32mp25-rifsc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gatien Chevallier <gatien.chevallier@foss.st.com>
19 - RISC registers associated with RISUP logic (resource isolation device unit
20 for peripherals), assign all non-RIF aware peripherals to zero, one or
22 - RIMC registers: associated with RIMU logic (resource isolation master
23 unit), assign all non RIF-aware bus master to one security domain by
25 Alternatively, the RISUP logic controlling the device port access to a
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| /Documentation/devicetree/bindings/gpio/ |
| D | nvidia,tegra186-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra186-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 Tegra186 contains two GPIO controllers; a main controller and an "AON"
15 controller. This binding document applies to both controllers. The register
16 layouts for the controllers share many similarities, but also some
25 a) Security registers, which allow configuration of allowed access to the
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| /Documentation/driver-api/ |
| D | edac.rst | 5 ----------------------------------------
8 *sockets, *socket sets*, *banks*, *rows*, *chip-select rows*, *channels*,
43 It is typically the highest hierarchy on a Fully-Buffered DIMM memory
52 * Single-channel
55 only. E. g. if the data is 64 bits-wide, the data flows to the CPU using
56 one 64 bits parallel access. Typically used with SDR, DDR, DDR2 and DDR3
57 memories. FB-DIMM and RAMBUS use a different concept for channel, so
60 * Double-channel
63 dimms, accessed at the same time. E. g. if the DIMM is 64 bits-wide (72
65 access.
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | intel,ixp4xx-expansion-bus-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/intel,ixp4xx-expansion-bus-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The IXP4xx expansion bus controller handles access to devices on the
11 memory-mapped expansion bus on the Intel IXP4xx family of system on chips,
15 - Linus Walleij <linus.walleij@linaro.org>
19 pattern: '^bus@[0-9a-f]+$'
23 - enum:
24 - intel,ixp42x-expansion-bus-controller
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| D | st,stm32-fmc2-ebi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped
14 - to translate AXI transactions into the appropriate external device
16 - to meet the access time requirements of the external devices
19 Select. The FMC2 performs only one access at a time to an external device.
22 - Christophe Kerello <christophe.kerello@foss.st.com>
27 - st,stm32mp1-fmc2-ebi
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| D | intel,ixp4xx-expansion-peripheral-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The IXP4xx expansion bus controller handles access to devices on the
11 memory-mapped expansion bus on the Intel IXP4xx family of system on chips,
15 - Linus Walleij <linus.walleij@linaro.org>
18 intel,ixp4xx-eb-t1:
23 intel,ixp4xx-eb-t2:
28 intel,ixp4xx-eb-t3:
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| /Documentation/devicetree/bindings/fsi/ |
| D | ibm,fsi2spi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-or-later)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: IBM FSI-attached SPI controllers
10 - Eddie James <eajames@linux.ibm.com>
15 access to a number of SPI controllers.
20 - ibm,fsi2spi
24 - description: FSI slave address
26 "#address-cells":
29 "#size-cells":
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| D | fsi-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fsi/fsi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Eddie James <eajames@linux.ibm.com>
14 FSI bus is connected to a CFAM (Common FRU Access Macro) which contains
15 various engines such as I2C controllers, SPI controllers, etc.
18 "#address-cells":
21 "#size-cells":
24 '#interrupt-cells':
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| /Documentation/i2c/busses/ |
| D | scx200_acb.rst | 5 Author: Christer Weinigel <wingel@nano-system.com>
7 The driver supersedes the older, never merged driver named i2c-nscacb.
10 -----------------
13 Base addresses for the ACCESS.bus controllers on SCx200 and SC1100 devices
20 -----------
22 Enable the use of the ACCESS.bus controller on the Geode SCx200 and
25 Device-specific notes
26 ---------------------
|
| /Documentation/devicetree/bindings/spi/ |
| D | spi-orion.txt | 4 - compatible : should be on of the following:
5 - "marvell,orion-spi" for the Orion, mv78x00, Kirkwood and Dove SoCs
6 - "marvell,armada-370-spi", for the Armada 370 SoCs
7 - "marvell,armada-375-spi", for the Armada 375 SoCs
8 - "marvell,armada-380-spi", for the Armada 38x SoCs
9 - "marvell,armada-390-spi", for the Armada 39x SoCs
10 - "marvell,armada-xp-spi", for the Armada XP SoCs
11 - reg : offset and length of the register set for the device.
13 the SPI direct access mode that some of the Marvell SoCs support
14 additionally to the normal indirect access (PIO) mode. The values
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| D | st,stm32-spi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/st,stm32-spi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 the Serial Peripheral Interface. It supports full-duplex, half-duplex and
13 from 4 to 32-bit data size.
16 - Erwan Leray <erwan.leray@foss.st.com>
17 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
20 - $ref: spi-controller.yaml#
25 - st,stm32f4-spi
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| /Documentation/gpu/ |
| D | tegra.rst | 11 supports the built-in GPU, comprised of the gr2d and gr3d engines. Starting
18 - A host1x driver that provides infrastructure and access to the host1x
21 - A KMS driver that supports the display controllers as well as a number of
24 - A set of custom userspace IOCTLs that can be used to submit jobs to the
40 device using a driver-provided function which will set up the bits specific to
48 -------------------------------
50 .. kernel-doc:: include/linux/host1x.h
52 .. kernel-doc:: drivers/gpu/host1x/bus.c
56 --------------------------
58 .. kernel-doc:: drivers/gpu/host1x/syncpt.c
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| /Documentation/admin-guide/gpio/ |
| D | gpio-aggregator.rst | 1 .. SPDX-License-Identifier: GPL-2.0-only
11 -----------------------------
13 GPIO controllers are exported to userspace using /dev/gpiochip* character
14 devices. Access control to these devices is provided by standard UNIX file
15 system permissions, on an all-or-nothing basis: either a GPIO controller is
18 The GPIO Aggregator provides access control for a set of one or more GPIOs, by
25 Aggregated GPIO controllers are instantiated and destroyed by writing to
26 write-only attribute files in sysfs.
28 /sys/bus/platform/drivers/gpio-aggregator/
35 .. code-block:: none
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| /Documentation/core-api/ |
| D | debugging-via-ohci1394.rst | 2 Using physical DMA provided by OHCI-1394 FireWire controllers for debugging
6 ------------
8 Basically all FireWire controllers which are in use today are compliant
9 to the OHCI-1394 specification which defines the controller to be a PCI
12 PCI-Bus master DMA after applying filters defined by the OHCI-1394 driver.
15 ask the OHCI-1394 controller to perform read and write requests on
25 With most FireWire controllers, memory access is limited to the low 4 GB
28 hardware such as x86, x86-64 and PowerPC.
30 At least LSI FW643e and FW643e2 controllers are known to support access to
34 Together with a early initialization of the OHCI-1394 controller for debugging,
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| /Documentation/admin-guide/ |
| D | cgroup-v2.rst | 1 .. _cgroup-v2:
11 conventions of cgroup v2. It describes all userland-visible aspects
14 v1 is available under :ref:`Documentation/admin-guide/cgroup-v1/index.rst <cgroup-v1>`.
19 1-1. Terminology
20 1-2. What is cgroup?
22 2-1. Mounting
23 2-2. Organizing Processes and Threads
24 2-2-1. Processes
25 2-2-2. Threads
26 2-3. [Un]populated Notification
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| /Documentation/misc-devices/ |
| D | c2port.rst | 1 .. SPDX-License-Identifier: GPL-2.0
23 --------
26 C2 Interface used for in-system programming of micro controllers.
28 By using this driver you can reprogram the in-system flash without EC2
33 ----------
38 - AN127: FLASH Programming via the C2 Interface at
41 - C2 Specification at
45 banging) designed to enable in-system programming, debugging, and
46 boundary-scan testing on low pin-count Silicon Labs devices. Currently
51 ----------------
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | pamu.txt | 1 Freescale Peripheral Management Access Unit (PAMU) Device Tree Binding
5 The PAMU is an I/O MMU that provides device-to-memory access control and
10 - compatible : <string>
11 First entry is a version-specific string, such as
12 "fsl,pamu-v1.0". The second is "fsl,pamu".
13 - ranges : <prop-encoded-array>
17 physically present PAMU controllers. For example, for
20 - interrupts : <prop-encoded-array>
22 interrupt, used for reporting access violations. The second
25 - #address-cells: <u32>
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| /Documentation/admin-guide/media/ |
| D | remote-controller.rst | 1 .. SPDX-License-Identifier: GPL-2.0
12 Most analog and digital TV boards support remote controllers. Several of
22 the `v4l-utils <https://git.linuxtv.org/v4l-utils.git/>`_. It provides
23 two tools to handle remote controllers:
25 - ir-keytable: provides a way to query the remote controller, list the
26 protocols it supports, enable in-kernel support for IR decoder or
29 - ir-ctl: provide tools to handle remote controllers that support raw mode
32 Usually, the remote controller module is auto-loaded when the TV card is
34 ir-kbd-i2c module.
44 applications to access the remote via /dev/input/event<n> devices.
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| /Documentation/devicetree/bindings/media/ |
| D | st,stm32mp25-video-codec.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/st,stm32mp25-video-codec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hugues Fruchet <hugues.fruchet@foss.st.com>
21 - st,stm32mp25-vdec
22 - st,stm32mp25-venc
33 access-controllers:
38 - compatible
39 - reg
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| /Documentation/devicetree/bindings/phy/ |
| D | phy-da8xx-usb.txt | 1 TI DA8xx/OMAP-L1xx/AM18xx USB PHY
4 - compatible: must be "ti,da830-usb-phy".
5 - #phy-cells: must be 1.
8 controllers on DA8xx SoCs. Consumers of this device should use index 0 for
11 It also requires a "syscon" node with compatible = "ti,da830-cfgchip", "syscon"
12 to access the CFGCHIP2 register.
17 compatible = "ti,da830-cfgchip", "syscon";
21 usb_phy: usb-phy {
22 compatible = "ti,da830-usb-phy";
23 #phy-cells = <1>;
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | ti,keystone-irq.txt | 10 - compatible: should be "ti,keystone-irq"
11 - ti,syscon-dev : phandle and offset pair. The phandle to syscon used to
12 access device control registers and the offset inside
14 - interrupt-controller : Identifies the node as an interrupt controller
15 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
17 - interrupts: interrupt reference to primary interrupt controller
20 Interrupt Controllers bindings used by client devices.
24 compatible = "ti,keystone-irq";
25 ti,syscon-dev = <&devctrl 0x2a0>;
27 interrupt-controller;
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| /Documentation/devicetree/bindings/net/ |
| D | microchip,lan8650.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip LAN8650/1 10BASE-T1S MACPHY Ethernet Controllers
10 - Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
13 The LAN8650/1 combines a Media Access Controller (MAC) and an Ethernet
14 PHY to enable 10BASE‑T1S networks. The Ethernet Media Access Controller
16 with the IEEE 802.3 standard and a 10BASE-T1S physical layer transceiver
18 the MAC-PHY is specified in the OPEN Alliance 10BASE-T1x MACPHY Serial
22 - $ref: /schemas/net/ethernet-controller.yaml#
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| /Documentation/ABI/testing/ |
| D | sysfs-class-scsi_host | 7 Storage Control Unit embeds up to two 4-port controllers in
8 a single PCI device. The controllers are enumerated in order
19 feature of HP Smart Array RAID controllers using the hpsa
22 of a logical drive, bypassing the controllers firmware RAID
34 Contact: linux-ide@vger.kernel.org
60 a) It does not use host-initiated slumber mode, but it does
61 allow device-initiated slumber
68 Contact: linux-ide@vger.kernel.org
79 protocol that is being used by the driver (for eg. LED, SAF-TE,
80 SES-2, SGPIO etc).
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