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/Documentation/devicetree/bindings/mtd/
Dst,stm32-fmc2-nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/st,stm32-fmc2-nand.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <christophe.kerello@foss.st.com>
15 - st,stm32mp15-fmc2
16 - st,stm32mp1-fmc2-nfc
17 - st,stm32mp25-fmc2-nfc
28 - description: tx DMA channel
29 - description: rx DMA channel
[all …]
Dgpio-control-nand.txt4 read/write the NAND commands and data and GPIO pins for the control
8 - compatible : "gpio-control-nand"
9 - reg : should specify localbus chip select and size used for the chip. The
10 resource describes the data bus connected to the NAND flash and all accesses
12 - #address-cells, #size-cells : Must be present if the device has sub-nodes
14 - gpios : Specifies the GPIO pins to control the NAND device. The order of
18 - bank-width : Width (in bytes) of the device. If not present, the width
20 - chip-delay : chip dependent delay for transferring data from array to
22 - gpio-control-nand,io-sync-reg : A 64-bit physical address for a read
24 the GPIO's and the NAND flash data bus. If present, then after changing
[all …]
/Documentation/misc-devices/
Dmax6875.rst13 Datasheet: http://pdfserv.maxim-ic.com/en/ds/MAX6874-MAX6875.pdf
19 -----------
21 The Maxim MAX6875 is an EEPROM-programmable power-supply sequencer/supervisor.
33 - vin gpi vout
43 -------------
45 eeprom - 512 bytes of user-defined EEPROM space.
49 ---------------
55 The driver does not probe any address, so you explicitly instantiate the
61 $ echo max6875 0x50 > /sys/bus/i2c/devices/i2c-0/new_device
63 The MAX6874/MAX6875 ignores address bit 0, so this driver attaches to multiple
[all …]
Duacce.rst1 .. SPDX-License-Identifier: GPL-2.0
4 ---------------------
6 Uacce (Unified/User-space-access-intended Accelerator Framework) targets to
8 So accelerator can access any data structure of the main cpu.
9 This differs from the data sharing between cpu and io device, which share
10 only data content rather than address.
11 Because of the unified address, hardware and user space of process can
12 share the same virtual address in the communication.
42 ------------
44 Uacce is the kernel module, taking charge of iommu and address sharing.
[all …]
/Documentation/devicetree/bindings/memory-controllers/
Dst,stm32-fmc2-ebi-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <christophe.kerello@foss.st.com>
11 - Marek Vasut <marex@denx.de>
14 st,fmc2-ebi-cs-transaction-type:
33 st,fmc2-ebi-cs-cclk-enable:
40 st,fmc2-ebi-cs-mux-enable:
41 description: Address/Data multiplexed on databus (valid only with
[all …]
Dmvebu-devbus.txt9 - compatible: Armada 370/XP SoC are supported using the
10 "marvell,mvebu-devbus" compatible string.
13 "marvell,orion-devbus" compatible string.
15 - reg: A resource specifier for the register space.
16 This is the base address of a chip select within
20 - #address-cells: Must be set to 1
21 - #size-cells: Must be set to 1
22 - ranges: Must be set up to reflect the memory layout with four
23 integer values for each chip-select line in use:
24 0 <physical address of mapping> <size>
[all …]
/Documentation/arch/sparc/oradax/
Ddax-hv-api.txt3 Publication date 2017-09-25 08:21
5 Extracted via "pdftotext -f 547 -l 572 -layout sun4v_20170925.pdf"
13 …The following APIs provide access via the Hypervisor to hardware assisted data processing function…
16 live-migration and other system management activities.
18 36.1. Data Analytics Accelerator
19 …The Data Analytics Accelerator (DAX) functionality is a collection of hardware coprocessors that p…
20 …high speed processoring of database-centric operations. The coprocessors may support one or more of
21 …the following data query operations: search, extraction, compression, decompression, and translati…
24 …The DAX is a virtual device to sun4v guests, with supported data operations indicated by the virtu…
28 …e Completion Area and, unless execution order is specifically restricted through the use of serial-
[all …]
/Documentation/devicetree/bindings/bus/
Dnvidia,tegra20-gmi.txt10 - compatible : Should contain one of the following:
11 For Tegra20 must contain "nvidia,tegra20-gmi".
12 For Tegra30 must contain "nvidia,tegra30-gmi".
13 - reg: Should contain GMI controller registers location and length.
14 - clocks: Must contain an entry for each entry in clock-names.
15 - clock-names: Must include the following entries: "gmi"
16 - resets : Must contain an entry for each entry in reset-names.
17 - reset-names : Must include the following entries: "gmi"
18 - #address-cells: The number of cells used to represent physical base
19 addresses in the GMI address space. Should be 2.
[all …]
/Documentation/staging/
Drpmsg.rst17 flavor of real-time OS.
19 OMAP4, for example, has dual Cortex-A9, dual Cortex-M3 and a C64x+ DSP.
20 Typically, the dual cortex-A9 is running Linux in a SMP configuration,
25 hardware accelerators, and therefore are often used to offload CPU-intensive
28 These remote processors could also be used to control latency-sensitive
34 hardware accessible only by the remote processor, reserving kernel-controlled
37 Rpmsg is a virtio-based messaging bus that allows kernel drivers to communicate
56 and have a local ("source") rpmsg address, and remote ("destination") rpmsg
57 address.
60 a unique rpmsg local address (a 32-bit integer). This way when inbound messages
[all …]
/Documentation/admin-guide/mm/
Dconcepts.rst7 systems from MMU-less microcontrollers to supercomputers. The memory
12 address to a physical address.
23 address ranges. Besides, different CPU architectures, and even
25 of how these address ranges are defined.
33 protection and controlled sharing of data between processes.
36 address. When the CPU decodes an instruction that reads (or
38 address encoded in that instruction to a `physical` address that the
49 translation from a virtual address used by programs to the physical
50 memory address. The page tables are organized hierarchically.
56 register. When the CPU performs the address translation, it uses this
[all …]
/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
Dcpm.txt10 - compatible : "fsl,cpm1", "fsl,cpm2", or "fsl,qe".
11 - reg : A 48-byte region beginning with CPCR.
15 #address-cells = <1>;
16 #size-cells = <1>;
17 #interrupt-cells = <2>;
18 compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
24 - fsl,cpm-command : This value is ORed with the opcode and command flag
27 - fsl,cpm-brg : Indicates which baud rate generator the device
32 - reg : Unless otherwise specified, the first resource represents the
36 * Multi-User RAM (MURAM)
[all …]
/Documentation/scsi/
Dcxgb3i.rst1 .. SPDX-License-Identifier: GPL-2.0
11 series of products) support iSCSI acceleration and iSCSI Direct Data Placement
16 - iSCSI PDU digest generation and verification
19 Data digest into the PDUs.
21 Data digest of the PDUs.
23 - Direct Data Placement (DDP)
25 S3 h/w can directly place the iSCSI Data-In or Data-Out PDU's
26 payload into pre-posted final destination host-memory buffers based
27 on the Initiator Task Tag (ITT) in Data-In or Target Task Tag (TTT)
28 in Data-Out PDUs.
[all …]
/Documentation/admin-guide/RAS/
Daddress-translation.rst1 .. SPDX-License-Identifier: GPL-2.0
3 Address translation
7 -------
9 Zen-based AMD systems include a Data Fabric that manages the layout of
12 These devices may provide a "normalized", i.e. device physical, address
14 a system physical address for the kernel to action on the memory.
16 AMD Address Translation Library (CONFIG_AMD_ATL) provides translation for
19 Glossary of acronyms used in address translation for Zen-based systems
22 * COD = Cluster-on-Die
24 * DF = Data Fabric
/Documentation/hwmon/
Dabituguru-datasheet.rst6 datasheet from Abit. The data I have got on uGuru have I assembled through
11 mailing Windbond for help won't give any useful data about uGuru, as it is
14 Olle Sandberg <ollebull@gmail.com>, 2005-05-25
27 Hans de Goede <j.w.r.degoede@hhs.nl>, 28-01-2006
33 As far as known the uGuru is always placed at and using the (ISA) I/O-ports
34 0xE0 and 0xE4, so we don't have to scan any port-range, just check what the two
35 ports are holding for detection. We will refer to 0xE0 as CMD (command-port)
36 and 0xE4 as DATA because Abit refers to them with these names.
38 If DATA holds 0x00 or 0x08 and CMD holds 0x00 or 0xAC an uGuru could be
39 present. We have to check for two different values at data-port, because
[all …]
Dsmsc47b397.rst6 * SMSC LPC47B397-NC
8 * SMSC SCH5307-NS
14 Addresses scanned: none, address read from Super I/O config space
20 - Mark M. Hoffman <mhoffman@lightlink.com>
21 - Utilitek Systems, Inc.
25 The following specification describes the SMSC LPC47B397-NC [1]_ sensor chip
27 provided by Craig Kelly (In-Store Broadcast Network) and edited/corrected
30 .. [1] And SMSC SCH5307-NS and SCH5317, which have different device IDs but are
33 -------------------------------------------------------------------------
35 Methods for detecting the HP SIO and reading the thermal data on a dc7100
[all …]
/Documentation/i2c/busses/
Di2c-mlxcpld.rst2 Driver i2c-mlxcpld
11 - Master mode.
12 - One physical bus.
13 - Polling mode.
20 - Receive Byte/Block.
21 - Send Byte/Block.
22 - Read Byte/Block.
23 - Write Byte/Block.
28 CPBLTY 0x0 - capability reg.
29 Bits [6:5] - transaction length. b01 - 72B is supported,
[all …]
/Documentation/arch/s390/
Dmonreader.rst5 Date : 2004-Nov-26
33 See also "CP Command and Utility Reference" (SC24-6081-00) for more information
35 and Administration" (SC24-6116-00) for more information on DCSSes.
38 -----------
40 guest virtual storage around the address range of the DCSS.
45 address 0MB, the second is 200MB in size and begins at address 200MB,
50 -----------
51 Your guest virtual storage has to end below the starting address of the DCSS
53 value greater than the ending address of the DCSS.
78 Refer to the "z/VM Performance" book (SC24-6109-00) on how to create a monitor
[all …]
/Documentation/admin-guide/device-mapper/
Dvdo-design.rst1 .. SPDX-License-Identifier: GPL-2.0-only
4 Design of dm-vdo
7 The dm-vdo (virtual data optimizer) target provides inline deduplication,
8 compression, zero-block elimination, and thin provisioning. A dm-vdo target
12 production environments ever since. It was made open-source in 2017 after
14 dm-vdo. For usage, see vdo.rst in the same directory as this file.
25 The design of dm-vdo is based on the idea that deduplication is a two-part
26 problem. The first is to recognize duplicate data. The second is to avoid
27 storing multiple copies of those duplicates. Therefore, dm-vdo has two main
29 duplicate data, and a data store with a reference counted block map that
[all …]
/Documentation/devicetree/bindings/nvmem/
Dsc27xx-efuse.txt4 - compatible: Should be one of the following.
5 "sprd,sc2720-efuse"
6 "sprd,sc2721-efuse"
7 "sprd,sc2723-efuse"
8 "sprd,sc2730-efuse"
9 "sprd,sc2731-efuse"
10 - reg: Specify the address offset of efuse controller.
11 - hwlocks: Reference to a phandle of a hwlock provider node.
13 = Data cells =
22 spi-max-frequency = <26000000>;
[all …]
/Documentation/devicetree/bindings/spi/
Dsprd,spi-adi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/sprd,spi-adi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Orson Zhai <orsonzhai@gmail.com>
11 - Baolin Wang <baolin.wang7@gmail.com>
12 - Chunyan Zhang <zhang.lyra@gmail.com>
15 ADI is the abbreviation of Anolog-Digital interface, which is used to access
24 which means we can just link one analog chip address to one hardware channel,
25 then users can access the mapped analog chip address by this hardware channel
[all …]
/Documentation/core-api/
Dswiotlb.rst1 .. SPDX-License-Identifier: GPL-2.0
12 the CPU copies the data between the temporary buffer and the original target
19 These APIs use the device DMA attributes and kernel-wide settings to determine
24 Because the CPU copies data between the bounce buffer and the original target
30 ---------------
33 only provide 32-bit DMA addresses. By allocating bounce buffer memory below
40 directed to guest memory that is unencrypted. CoCo VMs set a kernel-wide option
44 data to/from the original target memory buffer. The CPU copying bridges between
52 the data being transferred. But if that memory occupies only part of an IOMMU
53 granule, other parts of the granule may contain unrelated kernel data. Since
[all …]
/Documentation/devicetree/bindings/gpio/
Dnetxbig-gpio-ext.txt5 - compatible: "lacie,netxbig-gpio-ext".
6 - addr-gpios: GPIOs representing the address register (LSB -> MSB).
7 - data-gpios: GPIOs representing the data register (LSB -> MSB).
8 - enable-gpio: latches the new configuration (address, data) on raising edge.
12 netxbig_gpio_ext: netxbig-gpio-ext {
13 compatible = "lacie,netxbig-gpio-ext";
15 addr-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH
18 data-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH
21 enable-gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>;
/Documentation/devicetree/bindings/nvmem/layouts/
Dkontron,sl28-vpd.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/layouts/kontron,sl28-vpd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVMEM layout of the Kontron SMARC-sAL28 vital product data
10 - Michael Walle <michael@walle.cc>
13 The vital product data (VPD) of the sl28 boards contains a serial
14 number and a base MAC address. The actual MAC addresses for the
15 on-board ethernet devices are derived from this base MAC address by
22 const: kontron,sl28-vpd
[all …]
/Documentation/ABI/testing/
Ddebugfs-intel-iommu13 IOMMU: dmar0 Register Base Address: 26be37000
24 IOMMU: dmar1 Register Base Address: fed90000
35 IOMMU: dmar2 Register Base Address: fed91000
60 IR table address:100900000
67 IR table address:100300000
76 IR table address:100900000
87 '-1' and other PASID related fields are invalid.
95 IOMMU dmar1: Root Table Address: 0x103027000
103 -1 0x0000000000000000:0x0000000000000000:0x0000000000000000
105 IOMMU dmar0: Root Table Address: 0x103028000
[all …]
/Documentation/networking/
Doa-tc6-framework.rst1 .. SPDX-License-Identifier: GPL-2.0+
4 OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface (TC6) Framework Support
8 ------------
11 single pair of conductors. The 10BASE-T1L (Clause 146) is a long reach
12 PHY supporting full duplex point-to-point operation over 1 km of single
13 balanced pair of conductors. The 10BASE-T1S (Clause 147) is a short reach
14 PHY supporting full / half duplex point-to-point operation over 15 m of
21 works in conjunction with the 10BASE-T1S PHY operating in multidrop mode.
23 The aforementioned PHYs are intended to cover the low-speed / low-cost
29 The MAC-PHY solution integrates an IEEE Clause 4 MAC and a 10BASE-T1x PHY
[all …]

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