Searched full:affected (Results 1 – 25 of 232) sorted by relevance
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| /Documentation/admin-guide/hw-vuln/ |
| D | indirect-target-selection.rst | 26 Affected CPUs
28 Below is the list of ITS affected CPUs [#f2]_ [#f3]_:
34 SKYLAKE_X (step >= 6) 06_55H Affected Affected
35 ICELAKE_X 06_6AH Not affected Affected
36 ICELAKE_D 06_6CH Not affected Affected
37 ICELAKE_L 06_7EH Not affected Affected
38 TIGERLAKE_L 06_8CH Not affected Affected
39 TIGERLAKE 06_8DH Not affected Affected
40 KABYLAKE_L (step >= 12) 06_8EH Affected Affected
41 KABYLAKE (step >= 13) 06_9EH Affected Affected
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| D | reg-file-data-sampling.rst | 11 Affected Processors
13 Below is the list of affected Intel processors [#f1]_:
33 RAPTORLAKE(06_B7H) codenamed Catlow are not affected. They are reported as
34 vulnerable in Linux because they share the same family/model with an affected
35 part. Unlike their affected counterparts, they do not enumerate RFDS_CLEAR or
37 affected and unaffected parts, but it is deemed not worth adding complexity as
44 mitigation strategy to force the CPU to clear the affected buffers before an
47 The microcode clears the affected CPU buffers when the VERW instruction is
53 before VMentry. None of the affected cores support SMT, so VERW is not required
58 Newer processors and microcode update on existing affected processors added new
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| D | processor_mmio_stale_data.rst | 9 are not affected. System environments using virtualization where MMIO access is
61 processors affected by FBSDP, this may expose stale data from the fill buffers
67 into client core fill buffers, processors affected by MFBDS can leak data from
77 Affected Processors
79 Not all the CPUs are affected by all the variants. For instance, most
83 Below is the list of affected Intel processors [#f1]_:
108 If a CPU is in the affected processor list, but not affected by a variant, it
115 Newer processors and microcode update on existing affected processors added new
122 Bit 13 - SBDR_SSDP_NO - When set, processor is not affected by either the
125 Bit 14 - FBSDP_NO - When set, processor is not affected by the Fill Buffer
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| D | mds.rst | 8 Affected processors
23 Whether a processor is affected or not can be read out from the MDS
26 Not all processors are affected by all variants of MDS, but the mitigation
100 * - 'Not affected'
135 The kernel detects the affected CPUs and the presence of the microcode
138 If a CPU is affected and the microcode is available, then the kernel
148 The mitigation for MDS clears the affected CPU buffers on return to user
152 is only affected by MSBDS and not any other MDS variant, because the
155 For CPUs which are only affected by MSBDS the user space, guest and idle
156 transition mitigations are sufficient and SMT is not affected.
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| D | vmscape.rst | 13 Affected processors
16 The following CPU families are affected by VMSCAPE:
20 - Cascade Lake generation - (Parts affected by ITS guest/host separation)
21 - Alder Lake and newer (Parts affected by BHI)
23 Note that, BHI affected parts that use BHB clearing software mitigation e.g.
75 * 'Not affected':
110 not known to be affected.
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| D | tsx_async_abort.rst | 10 Affected processors
19 Whether a processor is affected or not can be read out from the TAA
99 …- The CPU is affected by this vulnerability and the microcode and kernel mitigation are not applie…
118 * - 'Not affected'
119 - The CPU is not affected by this issue.
124 The kernel detects the affected CPUs and the presence of the microcode which is
125 required. If a CPU is affected and the microcode is available, then the kernel
135 Affected systems where the host has TAA microcode and TAA is mitigated by
152 off This option disables the TAA mitigation on affected platforms.
154 is affected, the system is vulnerable.
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| D | special-register-buffer-data-sampling.rst | 17 Affected processors
20 be affected.
22 A processor is affected by SRBDS if its Family_Model and stepping is
25 latter class of processors are only affected when Intel TSX is enabled
26 by software using TSX_CTRL_MSR otherwise they are not affected.
118 affected platforms.
130 Not affected Processor not vulnerable
141 affected but with no way to know if host
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| D | cross-thread-rsb.rst | 18 Affected processors
38 Affected SMT-capable processors support 1T and 2T modes of execution when SMT
46 In affected processors, the return address predictor (RAP) is partitioned
61 An attack can be mounted on affected processors by performing a series of CALL
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| D | gather_data_sampling.rst | 76 use the microcode mitigation when available or disable AVX on affected systems
89 Not affected Processor not vulnerable.
102 affected but with no way to know if host
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| D | srso.rst | 27 Affected processors
45 * 'Not affected':
115 not affected anymore and thus "safe RET" is not needed.
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| /Documentation/arch/x86/ |
| D | mds.rst | 74 thread case (SMT off): Force the CPU to clear the affected buffers.
78 the affected CPU buffers when the VERW instruction is executed.
83 VERW can be avoided. If the CPU is not affected by L1TF then VERW needs to
119 off Mitigation is disabled. Either the CPU is not affected or
122 full Mitigation is enabled. CPU is affected and MD_CLEAR is
125 vmwerv Mitigation is enabled. CPU is affected and MD_CLEAR is not
132 If the CPU is affected and mds=off is not supplied on the kernel command
143 on affected CPUs when the mitigation is not disabled on the kernel
174 cleared on affected CPUs when SMT is active. This addresses the
181 The idle clearing is enabled on CPUs which are only affected by MSBDS
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| D | tsx_async_abort.rst | 37 off Mitigation is disabled. Either the CPU is not affected or
43 verw Mitigation is enabled. CPU is affected and MD_CLEAR is
46 ucode needed Mitigation is enabled. CPU is affected and MD_CLEAR is not
53 If the CPU is affected and the "tsx_async_abort" kernel command line parameter is
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| /Documentation/process/ |
| D | embargoed-hardware-issues.rst | 46 While hardware security issues are often handled by the affected silicon
129 description of the problem and a list of any known affected silicon. If
130 your organization builds or distributes the affected hardware, we encourage
131 you to also consider what other hardware could be affected. The disclosing
132 party is responsible for contacting the affected silicon vendors in a
229 To allow the affected silicon vendors to work with their internal teams and
233 Designated representatives of the affected silicon vendors are
236 response team about the handover. The affected silicon vendor must
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| D | security-bugs.rst | 47 the reporter or an affected party for up to 7 calendar days from the start
87 mailing list UNTIL a fix is accepted by the affected code's maintainers
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| /Documentation/filesystems/ |
| D | quota.rst | 83 - major number of a device with the affected filesystem
85 - minor number of a device with the affected filesystem
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| /Documentation/devicetree/bindings/reset/ |
| D | reset.txt | 23 the DT node of each affected HW block, since if activated, an unrelated block
26 children of the bus are affected by the reset signal, or an individual HW
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| /Documentation/PCI/ |
| D | pci-error-recovery.rst | 18 pSeries boxes. A typical action taken is to disconnect the affected device,
22 offered, so that the affected PCI device(s) are reset and put back
24 between the affected device drivers and the PCI controller chip.
31 is reported as soon as possible to all affected device drivers,
129 every driver affected by the error.
174 thus, if one device sleeps/schedules, all devices are affected.
191 DMA), and then calls the mmio_enabled() callback on all affected
338 The platform will call the resume() callback on all affected device
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | actions,s500-pinctrl.yaml | 73 List of gpio pin groups affected by the functions specified in
123 List of gpio pin groups affected by the drive-strength property
141 List of gpio pins affected by the bias-pull-* and
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| /Documentation/arch/powerpc/ |
| D | dawr-power9.rst | 7 has no way to distinguish CI memory when configuring the DAWR, so on affected
10 Affected processor revisions
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-iio-light-isl29018 | 16 is less affected by the ambient IR noise variation.
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| D | sysfs-devices-state_synced | 21 at the time the kernel starts are not affected or limited in
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| /Documentation/devicetree/bindings/net/ |
| D | ethernet-phy-package.yaml | 14 and each Ethernet PHY is affected by the global configuration
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| D | maxlinear,gpy2xx.yaml | 27 Affected PHYs (as far as known) are GPY215B and GPY215C.
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| /Documentation/hwmon/ |
| D | aspeed-g6-pwm-tach.rst | 25 affected by fan signal glitch.
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| /Documentation/gpu/ |
| D | automated_testing.rst | 71 bug to the author of the affected driver, the board name or Device Tree name of
72 the board, the first kernel version affected, the IGT version used for tests,
119 affected by the change.
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