Searched full:ahb (Results 1 – 25 of 182) sorted by relevance
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| /Documentation/devicetree/bindings/soc/tegra/ |
| D | nvidia,tegra20-ahb.yaml | 4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-ahb.yaml#
11 title: NVIDIA Tegra AHB
17 - nvidia,tegra20-ahb
18 - nvidia,tegra30-ahb
21 - nvidia,tegra114-ahb
22 - nvidia,tegra124-ahb
23 - nvidia,tegra210-ahb
24 - const: nvidia,tegra30-ahb
37 ahb@6000c004 {
38 compatible = "nvidia,tegra20-ahb";
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| /Documentation/devicetree/bindings/clock/ |
| D | allwinner,sun5i-a13-ahb-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun5i-a13-ahb-clk.yaml#
7 title: Allwinner A13 AHB Clock
20 const: allwinner,sun5i-a13-ahb-clk
44 ahb@1c20054 {
46 compatible = "allwinner,sun5i-a13-ahb-clk";
49 clock-output-names = "ahb";
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| D | nspire-clock.txt | 5 "lsi,nspire-cx-ahb-divider" for the AHB divider in the CX model
6 "lsi,nspire-classic-ahb-divider" for the AHB divider in the older model
14 - clocks: For the "nspire-*-ahb-divider" compatible clocks, this is the parent
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| D | allwinner,sun4i-a10-ahb-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-ahb-clk.yaml#
7 title: Allwinner A10 AHB Clock
21 - allwinner,sun4i-a10-ahb-clk
51 const: allwinner,sun4i-a10-ahb-clk
82 ahb@1c20054 {
84 compatible = "allwinner,sun4i-a10-ahb-clk";
87 clock-output-names = "ahb";
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| D | allwinner,sun9i-a80-ahb-clk.yaml | 4 $id: http://devicetree.org/schemas/clock/allwinner,sun9i-a80-ahb-clk.yaml#
7 title: Allwinner A80 AHB Clock
20 const: allwinner,sun9i-a80-ahb-clk
46 compatible = "allwinner,sun9i-a80-ahb-clk";
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| D | qca,ath79-pll.txt | 3 The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
20 - clock-output-names: should be "cpu", "ddr", "ahb"
32 clock-output-names = "cpu", "ddr", "ahb";
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| D | starfive,jh7110-aoncrg.yaml | 24 - description: STG AXI/AHB
31 - description: STG AXI/AHB or GMAC0 RGMII RX
32 - description: APB Bus or STG AXI/AHB
40 - description: STG AXI/AHB
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| D | allwinner,sun4i-a10-gates-clk.yaml | 26 - const: allwinner,sun4i-a10-ahb-gates-clk
27 - const: allwinner,sun5i-a10s-ahb-gates-clk
28 - const: allwinner,sun5i-a13-ahb-gates-clk
29 - const: allwinner,sun7i-a20-ahb-gates-clk
100 compatible = "allwinner,sun4i-a10-ahb-gates-clk";
102 clocks = <&ahb>;
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| /Documentation/devicetree/bindings/iommu/ |
| D | nvidia,tegra30-smmu.txt | 10 - nvidia,ahb : phandle to the ahb bus connected to SMMU.
20 nvidia,ahb = <&ahb>;
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| /Documentation/devicetree/bindings/misc/ |
| D | intel,ixp4xx-ahb-queue-manager.yaml | 5 $id: http://devicetree.org/schemas/misc/intel,ixp4xx-ahb-queue-manager.yaml#
8 title: Intel IXP4xx AHB Queue Manager
14 The IXP4xx AHB Queue Manager maintains queues as circular buffers in
26 - const: intel,ixp4xx-ahb-queue-manager
48 compatible = "intel,ixp4xx-ahb-queue-manager";
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| /Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,geni-se.yaml | 95 - const: s-ahb
99 - description: Slave AHB Clock
110 - const: m-ahb
111 - const: s-ahb
115 - description: Master AHB Clock
116 - description: Slave AHB Clock
132 clock-names = "m-ahb", "s-ahb";
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-ath79.txt | 6 - clocks: phandle of the AHB clock.
7 - clock-names: has to be "ahb".
20 clock-names = "ahb";
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| /Documentation/devicetree/bindings/rng/ |
| D | starfive,jh7110-trng.yaml | 26 - description: AHB reference clock
31 - const: ahb
55 clock-names = "hclk", "ahb";
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| D | rockchip,rk3568-rng.yaml | 26 - description: TRNG AHB clock
31 - const: ahb
56 clock-names = "core", "ahb";
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| /Documentation/devicetree/bindings/pci/ |
| D | qcom,pcie.yaml | 240 - const: iface # Configuration AHB clock
251 - const: ahb # AHB reset
274 - const: iface # Configuration AHB clock
315 - const: ahb # AHB reset
316 - const: phy_ahb # PHY AHB reset
355 - const: ahb # AHB clock
367 - const: ahb # AHB Reset
399 - const: ahb # AHB Reset
416 - const: iface # AHB clock
430 - const: ahb # AHB reset
[all …]
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| /Documentation/devicetree/bindings/crypto/ |
| D | fsl-imx-sahara.yaml | 30 - description: Sahara AHB clock
35 - const: ahb
73 clock-names = "ipg", "ahb";
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| D | starfive,jh7110-crypto.yaml | 25 - description: AHB reference clock
30 - const: ahb
89 clock-names = "hclk", "ahb";
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| D | allwinner,sun4i-a10-crypto.yaml | 44 - const: ahb
61 const: ahb
92 clock-names = "ahb", "mod";
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| /Documentation/devicetree/bindings/mtd/ |
| D | allwinner,sun4i-a10-nand.yaml | 34 - const: ahb
41 const: ahb
100 clock-names = "ahb", "mod";
102 reset-names = "ahb";
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| /Documentation/devicetree/bindings/usb/ |
| D | renesas,rzn1-usbf.yaml | 28 - description: Internal bus clock (AHB) for Function
29 - description: Internal bus clock (AHB) for Power Management
42 - description: The USBF AHB-EPC interrupt
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| /Documentation/devicetree/bindings/watchdog/ |
| D | alphascale,asm9260-wdt.yaml | 25 - description: ahb gate
30 - const: ahb
66 clock-names = "mod", "ahb";
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| /Documentation/devicetree/bindings/media/ |
| D | nxp,dw100.yaml | 35 - description: The AHB clock
40 - const: ahb
67 clock-names = "axi", "ahb";
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| D | rockchip,vdec.yaml | 35 - description: The Video Decoder AHB interface clock
42 - const: ahb
78 clock-names = "axi", "ahb", "cabac", "core";
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| D | coda.yaml | 40 - description: AHB interface clock
45 - const: ahb
105 clock-names = "per", "ahb";
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| /Documentation/devicetree/bindings/phy/ |
| D | qcom,usb-ss.yaml | 29 - description: PHY AHB clock
35 - const: ahb
76 clock-names = "ref", "ahb", "pipe";
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