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/Documentation/devicetree/bindings/ata/
Dahci-platform.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/ata/ahci-platform.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AHCI SATA Controller
10 SATA nodes are defined to describe on-chip Serial ATA controllers.
13 It is possible, but not required, to represent each port as a sub-node.
14 It allows to enable each port independently when dealing with multiple
18 - Hans de Goede <hdegoede@redhat.com>
19 - Jens Axboe <axboe@kernel.dk>
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Dahci-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ahci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common Properties for Serial ATA AHCI controllers
10 - Hans de Goede <hdegoede@redhat.com>
11 - Damien Le Moal <dlemoal@kernel.org>
14 This document defines device tree properties for a common AHCI SATA
18 document doesn't constitute a DT-node binding by itself but merely
19 defines a set of common properties for the AHCI-compatible devices.
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Dsnps,dwc-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/snps,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller
10 - Serge Semin <fancer.lancer@gmail.com>
14 implementation of the AHCI SATA controller.
20 - snps,dwc-ahci
21 - snps,spear-ahci
23 - compatible
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Drockchip,dwc-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/rockchip,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller for Rockchip devices
10 - Serge Semin <fancer.lancer@gmail.com>
14 implementation of the AHCI SATA controller found in Rockchip
22 - rockchip,rk3568-dwc-ahci
23 - rockchip,rk3588-dwc-ahci
25 - compatible
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Dbrcm,sata-brcm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/brcm,sata-brcm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom SATA3 AHCI Controller
10 SATA nodes are defined to describe on-chip Serial ATA controllers.
14 - Florian Fainelli <f.fainelli@gmail.com>
17 - $ref: ahci-common.yaml#
22 - items:
23 - enum:
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Dsnps,dwc-ahci-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/snps,dwc-ahci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller properties
10 - Serge Semin <fancer.lancer@gmail.com>
14 AHCI controller properties.
19 - $ref: ahci-common.yaml#
30 Basic DWC AHCI SATA clock sources like application AXI/AHB BIU clock,
31 PM-alive clock, RxOOB detection clock, embedded PHYs reference (Rx/Tx)
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Dbaikal,bt1-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/baikal,bt1-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Baikal-T1 SoC AHCI SATA controller
10 - Serge Semin <fancer.lancer@gmail.com>
13 AHCI SATA controller embedded into the Baikal-T1 SoC is based on the
14 DWC AHCI SATA v4.10a IP-core.
17 - $ref: snps,dwc-ahci-common.yaml#
21 const: baikal,bt1-ahci
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Dsata_highbank.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Calxeda AHCI SATA Controller
10 The Calxeda SATA controller mostly conforms to the AHCI interface
15 - Andre Przywara <andre.przywara@arm.com>
19 const: calxeda,hb-ahci
27 dma-coherent: true
29 calxeda,pre-clocks:
35 calxeda,post-clocks:
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Dceva,ahci-1v84.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ceva,ahci-1v84.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ceva AHCI SATA Controller
10 - Mubin Sayyed <mubin.sayyed@amd.com>
11 - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
14 The Ceva SATA controller mostly conforms to the AHCI interface with some
15 special extensions to add functionality, is a high-performance dual-port
16 SATA host controller with an AHCI compliant command layer which supports
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Dahci-st.txt6 - compatible : Must be "st,ahci"
7 - reg : Physical base addresses and length of register sets
8 - interrupts : Interrupt associated with the SATA device
9 - interrupt-names : Associated name must be; "hostc"
10 - clocks : The phandle for the clock
11 - clock-names : Associated name must be; "ahci_clk"
12 - phys : The phandle for the PHY port
13 - phy-names : Associated name must be; "ahci_phy"
16 - resets : The power-down, soft-reset and power-reset lines of SATA IP
17 - reset-names : Associated names must be; "pwr-dwn", "sw-rst" and "pwr-rst"
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/Documentation/ABI/testing/
Dsysfs-class-scsi_host7 Storage Control Unit embeds up to two 4-port controllers in
34 Contact: linux-ide@vger.kernel.org
60 a) It does not use host-initiated slumber mode, but it does
61 allow device-initiated slumber
68 Contact: linux-ide@vger.kernel.org
72 as defined in the AHCI spec.
79 protocol that is being used by the driver (for eg. LED, SAF-TE,
80 SES-2, SGPIO etc).
87 Contact: linux-ide@vger.kernel.org
94 Contact: linux-ide@vger.kernel.org
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