| /Documentation/devicetree/bindings/bus/ |
| D | baikal,bt1-apb.yaml | 5 $id: http://devicetree.org/schemas/bus/baikal,bt1-apb.yaml#
8 title: Baikal-T1 APB-bus
15 which routes them to the AXI-APB bridge. This interface is a single master
17 addressed APB slave devices. In case of any APB protocol collisions, slave
19 reported to the APB terminator (APB Errors Handler Block).
27 const: baikal,bt1-apb
31 - description: APB EHB MMIO registers
32 - description: APB MMIO region with no any device mapped
44 - description: APB reference clock
52 - description: APB domain reset line
[all …]
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | csky,apb-intc.txt | 2 C-SKY APB Interrupt Controller
5 C-SKY APB Interrupt Controller is a simple soc interrupt controller
6 on the apb bus and we only use it as root irq controller.
8 - csky,apb-intc is used in a lot of csky fpgas and socs, it support 64 irq nums.
9 - csky,dual-apb-intc consists of 2 apb-intc and 128 irq nums supported.
16 Description: Describes APB interrupt controller
23 Definition: must be "csky,apb-intc"
24 "csky,dual-apb-intc"
44 compatible = "csky,apb-intc";
51 compatible = "csky,dual-apb-intc";
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| D | snps,dw-apb-ictl.txt | 1 Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
3 Synopsys DesignWare provides interrupt controller IP for APB known as
5 APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt
9 - compatible: shall be "snps,dw-apb-ictl"
29 compatible = "snps,dw-apb-ictl";
39 compatible = "snps,dw-apb-ictl";
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| /Documentation/devicetree/bindings/timer/ |
| D | snps,dw-apb-timer.yaml | 4 $id: http://devicetree.org/schemas/timer/snps,dw-apb-timer.yaml#
7 title: Synopsys DesignWare APB Timer
15 - const: snps,dw-apb-timer
17 - snps,dw-apb-timer-sp
18 - snps,dw-apb-timer-osc
34 - description: APB interface clock source
63 compatible = "snps,dw-apb-timer";
71 compatible = "snps,dw-apb-timer";
79 compatible = "snps,dw-apb-timer";
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| /Documentation/devicetree/bindings/phy/ |
| D | intel,keembay-phy-usb.yaml | 18 - description: USB APB CPR (clock, power, reset) register
19 - description: USB APB slave register
23 - const: cpr-apb-base
24 - const: slv-apb-base
42 reg-names = "cpr-apb-base", "slv-apb-base";
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| D | rockchip,rk3588-hdptx-phy.yaml | 23 - description: APB clock
28 - const: apb
39 - description: APB reset line
49 - const: apb
85 clock-names = "ref", "apb";
91 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", "lcpll";
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| D | intel,lgm-usb-phy.yaml | 25 - description: APB BUS reset
31 - const: apb
56 reset-names = "phy", "apb", "phy31";
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| D | phy-rockchip-naneng-combphy.yaml | 24 - description: apb clock
30 - const: apb
41 - const: apb
135 clock-names = "ref", "apb", "pipe";
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| /Documentation/devicetree/bindings/usb/ |
| D | starfive,jh7110-usb.yaml | 41 - description: APB clock
43 - description: UTMI APB clock
49 - const: apb
56 - description: APB clock reset
58 - description: UTMI APB clock reset
63 - const: apb
97 clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
102 reset-names = "pwrup", "apb", "axi", "utmi_apb";
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| /Documentation/devicetree/bindings/serial/ |
| D | snps-dw-apb-uart.yaml | 4 $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
55 - const: snps,dw-apb-uart
58 - brcm,bcm11351-dw-apb-uart
59 - brcm,bcm21664-dw-apb-uart
60 - const: snps,dw-apb-uart
66 - const: snps,dw-apb-uart
67 - const: snps,dw-apb-uart
143 compatible = "snps,dw-apb-uart";
158 compatible = "snps,dw-apb-uart";
169 compatible = "snps,dw-apb-uart";
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| /Documentation/devicetree/bindings/gpio/ |
| D | snps,dw-apb-gpio.yaml | 4 $id: http://devicetree.org/schemas/gpio/snps,dw-apb-gpio.yaml#
7 title: Synopsys DesignWare APB GPIO controller
23 const: snps,dw-apb-gpio
37 - description: APB interface clock source
54 const: snps,dw-apb-gpio-port
120 compatible = "snps,dw-apb-gpio";
126 compatible = "snps,dw-apb-gpio-port";
138 compatible = "snps,dw-apb-gpio-port";
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| /Documentation/devicetree/bindings/pwm/ |
| D | snps,dw-apb-timers-pwm2.yaml | 5 $id: http://devicetree.org/schemas/pwm/snps,dw-apb-timers-pwm2.yaml#
8 title: Synopsys DW-APB timers PWM controller
14 This describes the DesignWare APB timers module when used in the PWM
28 const: snps,dw-apb-timers-pwm2
62 compatible = "snps,dw-apb-timers-pwm2";
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| /Documentation/devicetree/bindings/clock/ |
| D | moxa,moxart-clock.txt | 7 MOXA ART SoCs allow to determine PLL output and APB frequencies
23 APB:
26 - compatible : Must be "moxa,moxart-apb-clock"
44 compatible = "moxa,moxart-apb-clock";
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| D | starfive,jh7110-aoncrg.yaml | 25 - description: APB Bus
32 - description: APB Bus or STG AXI/AHB
33 - description: GMAC0 GTX or APB Bus
41 - description: APB Bus
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| /Documentation/devicetree/bindings/spi/ |
| D | snps,dw-apb-ssi.yaml | 4 $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
57 - snps,dw-apb-ssi
64 - const: snps,dw-apb-ssi
68 const: amazon,alpine-dw-apb-ssi
72 - const: snps,dw-apb-ssi
94 - const: snps,dw-apb-ssi
99 - description: DW APB SSI controller memory mapped registers
109 - description: APB interface clock source
184 compatible = "snps,dw-apb-ssi";
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| /Documentation/devicetree/bindings/arm/ |
| D | arm,juno-fpga-apb-regs.yaml | 4 $id: http://devicetree.org/schemas/arm/arm,juno-fpga-apb-regs.yaml#
7 title: ARM Juno FPGA APB Registers
15 - const: arm,juno-fpga-apb-regs
46 compatible = "arm,juno-fpga-apb-regs", "syscon", "simple-mfd";
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| /Documentation/devicetree/bindings/pci/ |
| D | starfive,jh7110-pcie.yaml | 24 - description: APB clock
31 - const: apb
40 - description: PCIE APB reset
49 - const: apb
83 reg-names = "cfg", "apb";
104 clock-names = "noc", "tl", "axi_mst0", "apb";
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| /Documentation/devicetree/bindings/sound/ |
| D | starfive,jh7110-pwmdac.yaml | 30 - description: PWMDAC APB
35 - const: apb
40 description: PWMDAC APB
71 clock-names = "apb", "core";
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| /Documentation/devicetree/bindings/watchdog/ |
| D | starfive,jh7100-wdt.yaml | 41 - description: APB clock
46 - const: apb
78 - description: APB reset
90 clock-names = "apb", "core";
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| D | snps,dw-wdt.yaml | 63 DW APB Watchdog custom timer intervals - Timeout Period ranges (TOPs).
67 the timer expiration intervals supported by the DW APB Watchdog. Note
68 DW APB Watchdog IP-core might be synthesized with fixed TOP values,
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | mediatek,smi-common.yaml | 61 apb and smi are mandatory. the async is only for generation 1 smi HW.
65 - description: apb is Advanced Peripheral Bus clock, It's the clock for
101 - const: apb
120 - const: apb
146 - const: apb
167 - const: apb
183 clock-names = "apb", "smi";
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| D | mediatek,smi-larb.yaml | 46 apb and smi are mandatory. gals(global async local sync) is optional.
49 - description: apb is Advanced Peripheral Bus clock, It's the clock for
97 - const: apb
108 - const: apb
142 clock-names = "apb", "smi";
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| /Documentation/devicetree/bindings/dma/ |
| D | loongson,ls2x-apbdma.yaml | 7 title: Loongson LS2X APB DMA controller
10 The Loongson LS2X APB DMA controller is used for transferring data
11 between system memory and the peripherals on the APB bus.
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| /Documentation/devicetree/bindings/soc/imx/ |
| D | fsl,imx8mm-disp-blk-ctrl.yaml | 48 - const: csi-bridge-apb
51 - const: lcdif-apb
90 clock-names = "csi-bridge-axi", "csi-bridge-apb", "csi-bridge-core",
91 "lcdif-axi", "lcdif-apb", "lcdif-pix", "dsi-pclk",
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| /Documentation/devicetree/bindings/mtd/ |
| D | gpmi-nand.yaml | 127 - description: SoC gpmi apb clock
129 - description: SoC gpmi bch apb clock
149 - description: SoC gpmi bch apb clock
166 - description: SoC gpmi apb clock
168 - description: SoC gpmi bch apb clock
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