Searched full:apmixedsys (Results 1 – 18 of 18) sorted by relevance
| /Documentation/devicetree/bindings/clock/ |
| D | mediatek,apmixedsys.yaml | 4 $id: http://devicetree.org/schemas/clock/mediatek,apmixedsys.yaml#
14 The Mediatek apmixedsys controller provides PLLs to the system.
21 - mediatek,mt6797-apmixedsys
22 - mediatek,mt7622-apmixedsys
23 - mediatek,mt7981-apmixedsys
24 - mediatek,mt7986-apmixedsys
25 - mediatek,mt7988-apmixedsys
26 - mediatek,mt8135-apmixedsys
27 - mediatek,mt8173-apmixedsys
28 - mediatek,mt8516-apmixedsys
[all …]
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| D | mediatek,mt8195-sys-clock.yaml | 20 The apmixedsys provides most of PLLs which generated from SoC 26m.
30 - mediatek,mt8195-apmixedsys
65 apmixedsys: syscon@1000c000 {
66 compatible = "mediatek,mt8195-apmixedsys", "syscon";
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| D | mediatek,mt8192-sys-clock.yaml | 23 - mediatek,mt8192-apmixedsys
64 apmixedsys: syscon@1000c000 {
65 compatible = "mediatek,mt8192-apmixedsys", "syscon";
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| D | mediatek,mt8365-sys-clock.yaml | 13 The apmixedsys module provides most of PLLs which generated from SoC 26m.
23 - mediatek,mt8365-apmixedsys
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| D | mediatek,mt8186-sys-clock.yaml | 20 The apmixedsys provides most of PLLs which generated from SoC 26m.
33 - mediatek,mt8186-apmixedsys
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| D | mediatek,mt8188-sys-clock.yaml | 20 The apmixedsys provides most of PLLs which generated from SoC 26m.
30 - mediatek,mt8188-apmixedsys
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| D | mediatek,mt8186-fhctl.yaml | 56 clocks = <&apmixedsys CLK_APMIXED_MSDCPLL>;
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| /Documentation/devicetree/bindings/thermal/ |
| D | mediatek,thermal.yaml | 15 controls a mux in the apmixedsys register space via AHB bus accesses, so a
16 phandle to the APMIXEDSYS is also needed.
54 mediatek,apmixedsys:
56 description: A phandle to the APMIXEDSYS controller
77 - mediatek,apmixedsys
95 mediatek,apmixedsys = <&apmixedsys>;
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| /Documentation/devicetree/bindings/sound/ |
| D | mt8192-afe-pcm.yaml | 26 mediatek,apmixedsys:
28 description: The phandle of the mediatek apmixedsys controller
62 - mediatek,apmixedsys
84 mediatek,apmixedsys = <&apmixedsys>;
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| D | mt8186-afe-pcm.yaml | 28 mediatek,apmixedsys:
30 description: The phandle of the mediatek apmixedsys controller
101 - mediatek,apmixedsys
120 mediatek,apmixedsys = <&apmixedsys>;
129 <&apmixedsys 12>, //CLK_APMIXED_APLL1
131 <&apmixedsys 13>, //CLK_APMIXED_APLL2
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| D | mediatek,mt8188-afe.yaml | 194 <&apmixedsys 9>, //CLK_APMIXED_APLL1
195 <&apmixedsys 10>, //CLK_APMIXED_APLL2
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| D | mediatek,mt7986-afe.yaml | 156 <&apmixedsys CLK_APMIXED_APLL2>,
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| /Documentation/devicetree/bindings/media/ |
| D | mediatek,vcodec-decoder.yaml | 174 clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
179 <&apmixedsys CLK_APMIXED_VENCPLL>,
193 <&apmixedsys CLK_APMIXED_VCODECPLL>,
194 <&apmixedsys CLK_APMIXED_VENCPLL>;
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| /Documentation/devicetree/bindings/cpufreq/ |
| D | cpufreq-mediatek.txt | 71 <&apmixedsys CLK_APMIXED_MAINPLL>;
193 <&apmixedsys CLK_APMIXED_MAINPLL>;
205 <&apmixedsys CLK_APMIXED_MAINPLL>;
217 <&apmixedsys CLK_APMIXED_MAINPLL>;
229 <&apmixedsys CLK_APMIXED_MAINPLL>;
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| /Documentation/devicetree/bindings/phy/ |
| D | mediatek,hdmi-phy.yaml | 87 clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
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| D | mediatek,tphy.yaml | 304 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>, <&clk48m>;
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| /Documentation/devicetree/bindings/display/mediatek/ |
| D | mediatek,dpi.yaml | 105 <&apmixedsys CLK_APMIXED_TVDPLL>;
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| /Documentation/devicetree/bindings/net/ |
| D | mediatek,net.yaml | 440 <&apmixedsys CLK_APMIXED_ETH2PLL>;
536 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
537 <&apmixedsys CLK_APMIXED_SGMPLL>;
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