Searched full:architected (Results 1 – 15 of 15) sorted by relevance
| /Documentation/devicetree/bindings/timer/ |
| D | arm,arch_timer.yaml | 7 title: ARM architected timer
13 ARM cores may have a per-core architected timer, which provides per-cpu timers,
14 or a memory mapped architected timer, which provides up to 8 frames with a
17 The per-core architected timer is attached to a GIC to deliver its
95 supported for 32-bit systems which follow the ARMv7 architected reset
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| D | arm,arch_timer_mmio.yaml | 7 title: ARM memory mapped architected timer
14 ARM cores may have a memory mapped architected timer, which provides up to 8
52 supported for 32-bit systems which follow the ARMv7 architected reset
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| /Documentation/arch/arm64/ |
| D | amu.rst | 39 The Activity Monitors architecture provides space for up to 16 architected
41 implement additional architected event counters.
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| D | booting.rst | 185 System caches which respect the architected cache maintenance by VA
187 System caches which do not respect architected cache maintenance by VA
190 - Architected timers
206 All writable architected system registers at or below the exception
436 The requirements described above for CPU mode, caches, MMUs, architected
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| D | elf_hwcaps.rst | 15 architected discovery mechanism available to userspace code at EL0. The
46 which are described by architected ID registers inaccessible to
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| /Documentation/devicetree/bindings/perf/ |
| D | arm,smmu-v3-pmcg.yaml | 16 architected and IMPLEMENTATION DEFINED event counters.
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| /Documentation/virt/kvm/arm/ |
| D | vcpu-features.rst | 18 Otherwise, all CPU features supported by KVM are described by the architected
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| /Documentation/admin-guide/perf/ |
| D | xgene-pmu.rst | 7 controller(s). These PMU devices are loosely architected to follow the
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| /Documentation/arch/powerpc/ |
| D | elf_hwcaps.rst | 167 The processor supports architected PMU events in the range 0xE0-0xFF.
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| D | cxlflash.rst | 338 the kernel's knowledge. When encountered, the user's architected
353 architected behavior for a user is to call into this ioctl to recover
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| D | ultravisor.rst | 140 non-architected registers. An attempt to write to them will cause a
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| /Documentation/devicetree/bindings/powerpc/ |
| D | ibm,powerpc-cpu-features.txt | 71 Node: A string describing an architected CPU feature, e.g., "floating-point".
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| /Documentation/PCI/ |
| D | acpi-info.rst | 50 These are all device-specific, non-architected things, so the only way a
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| /Documentation/virt/kvm/devices/ |
| D | vcpu.rst | 158 A value describing the architected timer interrupt number when connected to an
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| /Documentation/admin-guide/ |
| D | kernel-parameters.txt | 711 architected timer so that code using WFE-based polling
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