Searched full:architecturally (Results 1 – 17 of 17) sorted by relevance
| /Documentation/arch/arm64/ |
| D | amu.rst | 27 of four fixed and architecturally defined 64-bit event counters.
32 - Instructions retired: increments with every architecturally executed
|
| D | booting.rst | 15 level and exists only in secure mode. Both are architecturally optional.
|
| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,cpu-intc.yaml | 19 cores. The timer interrupt comes from an architecturally mandated real-
|
| /Documentation/devicetree/bindings/timer/ |
| D | arm,arch_timer_mmio.yaml | 51 registers, which contain their architecturally-defined reset values. Only
|
| D | arm,arch_timer.yaml | 94 registers, which contain their architecturally-defined reset values. Only
|
| /Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra30-mc.yaml | 15 Tegra30 Memory Controller architecturally consists of the following parts:
|
| /Documentation/virt/kvm/arm/ |
| D | pkvm.rst | 79 with the vCPU registers being initialised to their architecturally-defined
|
| /Documentation/arch/x86/ |
| D | entry_64.rst | 42 - Architecturally-defined exceptions like divide_error.
|
| /Documentation/devicetree/bindings/arm/ |
| D | arm,coresight-cti.yaml | 36 architecturally connected CTI an additional compatible string is used to
251 # v8 architecturally defined CTI - CPU + ETM connections generated by the
|
| /Documentation/virt/kvm/devices/ |
| D | arm-vgic-v3.rst | 108 architecturally defined behavior to allow software a full view of the
131 The GICD_STATUSR and GICR_STATUSR registers are architecturally defined such
|
| /Documentation/arch/arm/ |
| D | booting.rst | 225 peripherals and CPU resources for which this is architecturally
|
| /Documentation/trace/coresight/ |
| D | coresight-ect.rst | 48 the connections have an architecturally defined standard layout.
|
| D | coresight-etm4x-reference.rst | 822 data trace. As A-profile data trace is architecturally prohibited in ETMv4,
|
| /Documentation/admin-guide/hw-vuln/ |
| D | processor_mmio_stale_data.rst | 31 does not make stale data architecturally visible. Stale data must be propagated
|
| /Documentation/arch/loongarch/ |
| D | introduction.rst | 26 are not architecturally special. (Except ``$r1``, which is hard-wired as the
|
| /Documentation/admin-guide/mm/ |
| D | hugetlbpage.rst | 11 support 4K and 2M (1G if architecturally supported) page sizes, ia64
|
| /Documentation/virt/kvm/ |
| D | api.rst | 3473 - System registers: Reset to their architecturally defined
4004 Note: If any architecturally invalid key value is found in the given data then
7842 KVM_MSR_EXIT_REASON_INVAL intercept accesses that are architecturally
|