Searched +full:armada +full:- +full:8 +full:k +full:- +full:nand +full:- +full:controller (Results 1 – 3 of 3) sorted by relevance
| /Documentation/devicetree/bindings/mtd/ |
| D | marvell,nand-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/marvell,nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell NAND Flash Controller (NFC)
10 - Miquel Raynal <miquel.raynal@bootlin.com>
15 - items:
16 - const: marvell,armada-8k-nand-controller
17 - const: marvell,armada370-nand-controller
18 - enum:
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| /Documentation/devicetree/bindings/arm/marvell/ |
| D | cp110-system-controller.txt | 1 Marvell Armada CP110 System Controller
4 The CP110 is one of the two core HW blocks of the Marvell Armada 7K/8K
6 giving access to numerous features: clocks, pin-muxing and many other
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the CP110 system controller
14 SYSTEM CONTROLLER 0
18 -------
20 The Device Tree node representing this System Controller 0 provides a
23 - a set of core clocks
24 - a set of gateable clocks
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | mvebu-devbus.txt | 3 The Device Bus controller available in some Marvell's SoC allows to control
4 different types of standard memory and I/O devices such as NOR, NAND, and FPGA.
9 - compatible: Armada 370/XP SoC are supported using the
10 "marvell,mvebu-devbus" compatible string.
13 "marvell,orion-devbus" compatible string.
15 - reg: A resource specifier for the register space.
17 the controller's register space.
20 - #address-cells: Must be set to 1
21 - #size-cells: Must be set to 1
22 - ranges: Must be set up to reflect the memory layout with four
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