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/Documentation/devicetree/bindings/mtd/partitions/
Dnvmem-cells.yaml43 art: art@1200000 {
46 label = "art";
Dqcom,smem-part.yaml47 partition-art {
51 label = "0:art";
/Documentation/devicetree/bindings/dma/
Dmoxa,moxart-dma.txt1 MOXA ART DMA Controller
25 DMA clients connected to the MOXA ART DMA controller must use the format
/Documentation/crypto/
Darchitecture.rst249 The following ASCII art decomposes the kernel crypto API layers when
253 For other use cases of AEAD ciphers, the ASCII art applies as well, but
268 following ASCII art applies too. However, the decomposition of GCM into
272 Each block in the following ASCII art is an independent cipher instance
280 The ASCII art picture also indicates the call structure, i.e. who calls
320 the ASCII art above:
365 art picture above.
368 ASCII art picture above applies as well with the difference that only
375 depicted in the ASCII art picture above.
378 sha256_generic.c. The following ASCII art illustrates the
/Documentation/devicetree/bindings/media/
Dst,stm32-dma2d.yaml7 title: STMicroelectronics STM32 Chrom-Art Accelerator DMA2D
10 Chrom-ART Accelerator(DMA2D), graphical hardware accelerator
/Documentation/devicetree/bindings/watchdog/
Dmoxa,moxart-watchdog.txt1 MOXA ART Watchdog timer
/Documentation/devicetree/bindings/arm/
Dmoxart.yaml7 title: MOXA ART
/Documentation/devicetree/bindings/rtc/
Dmoxa,moxart-rtc.txt1 MOXA ART real-time clock
/Documentation/devicetree/bindings/mmc/
Dmoxa,moxart-mmc.txt1 MOXA ART MMC Host Controller Interface
/Documentation/sphinx/
Dkerneldoc-preamble.sty152 % For CJK ascii-art alignment
166 % For CJK ascii-art alignment
178 % For CJK ascii-art alignment (still misaligned for Hangul)
190 % For CJK ascii-art alignment
/Documentation/networking/
Dtc-actions-env-rules.rst25 #) Thou art responsible for freeing anything returned as being
/Documentation/devicetree/bindings/clock/
Dmoxa,moxart-clock.txt7 MOXA ART SoCs allow to determine PLL output and APB frequencies
/Documentation/arch/arm/sunxi/
Dclocks.rst6 about the sunxi clock system, as well as accompanying ASCII art when adequate.
/Documentation/driver-api/thermal/
Dintel_dptf.rst105 ACPI_THERMAL_GET_ART_LEN: Get length of ART table
109 ACPI_THERMAL_GET_ART_COUNT: Number of records in ART table
114 ACPI_THERMAL_GET_ART: Read binary ART table, length to read is
/Documentation/driver-api/gpio/
Dbt8xxgpio.rst24 The physical pinouts are drawn in the following ASCII art.
/Documentation/devicetree/bindings/spi/
Dspi-mux.yaml12 has chip selects available. An example setup is shown in ASCII art; the actual
/Documentation/admin-guide/media/
Dplatform-cardlist.rst62 stm32-dma2d STM32 Chrom-Art Accelerator Unit
/Documentation/scheduler/
Dsched-nice-design.rst20 understand it, the timeslice graph went like this (cheesy ASCII art
/Documentation/devicetree/bindings/arm/stm32/
Dstm32.yaml47 - st,stm32h750i-art-pi
/Documentation/trace/rv/
Ddeterministic_automata.rst133 using the dot utility, or into an ASCII art using graph-easy. For
/Documentation/process/
D5.Posting.rst81 up patches is a bit of an art; some developers spend a long time figuring
162 changelogs is a crucial but often-neglected art; it's worth spending
/Documentation/power/
Dsuspend-and-cpuhotplug.rst14 Well, a picture is worth a thousand words... So ASCII art follows :-)
/Documentation/sound/designs/
Dtimestamping.rst43 ascii-art, this could be represented as follows (for the playback
/Documentation/security/tpm/
Dtpm-security.rst24 The current state of the art for snooping the `TPM Genie`_ hardware
/Documentation/trace/
Dtimerlat-tracer.rst114 The art below illustrates a CPU timeline and how the timerlat tracer

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