Home
last modified time | relevance | path

Searched full:asserted (Results 1 – 25 of 94) sorted by relevance

1234

/Documentation/devicetree/bindings/bus/
Dnvidia,tegra20-gmi.txt46 If omitted it will be asserted with data.
56 - nvidia,snor-muxed-width: Number of cycles MUX address/data asserted on the
58 - nvidia,snor-hold-width: Number of cycles CE stays asserted after the
61 - nvidia,snor-adv-width: Number of cycles during which ADV stays asserted.
63 - nvidia,snor-ce-width: Number of cycles before CE is asserted.
65 - nvidia,snor-we-width: Number of cycles during which WE stays asserted.
67 - nvidia,snor-oe-width: Number of cycles during which OE stays asserted.
69 - nvidia,snor-wait-width: Number of cycles before READY is asserted.
Dqcom,ebi2.yaml117 is de-asserted, in order to avoid contention on the data bus.
128 data out is driven from the time WE is asserted until CS is
129 asserted. With a hold of 1 (value = 0), the CS stays active
177 respect to the cycle where ADV (address valid) is asserted.
/Documentation/ABI/testing/
Dsysfs-driver-ge-achc14 1 means the reset line is asserted, 0 means it's not
15 asserted. The file is read and writable.
/Documentation/devicetree/bindings/pci/
Dlayerscape-pcie-gen4.txt15 "intr": The interrupt that is asserted for controller interrupts
16 "aer": Asserted for aer interrupt when chip support the aer interrupt with
18 "pme": Asserted for pme interrupt when chip support the pme interrupt with
Dxlnx,nwl-pcie.yaml34 - description: interrupt asserted when miscellaneous interrupt is received
36 - description: interrupt asserted when a legacy interrupt is received
37 - description: msi1 interrupt asserted when an MSI is received
38 - description: msi0 interrupt asserted when an MSI is received
Dxlnx,xdma-host.yaml38 - description: interrupt asserted when miscellaneous interrupt is received.
39 - description: msi0 interrupt asserted when an MSI is received.
40 - description: msi1 interrupt asserted when an MSI is received.
/Documentation/devicetree/bindings/iio/adc/
Dadi,ad7780.yaml46 specified, it will be asserted during driver probe. As the
53 the ad778x chips. If specified, it will be asserted during
61 for the ad778x chips. If specified, it will be asserted
/Documentation/devicetree/bindings/reset/
Dst,stih407-picophyreset.yaml17 The actual action taken when softreset is asserted is hardware dependent.
18 However, when asserted it may not be possible to access the hardware's
Dst,stih407-powerdown.yaml19 The actual action taken when powerdown is asserted is hardware dependent.
20 However, when asserted it may not be possible to access the hardware's
Dst,sti-softreset.txt9 The actual action taken when softreset is asserted is hardware dependent.
10 However, when asserted it may not be possible to access the hardware's
Dimg,pistachio-reset.txt8 The actual action taken when soft reset is asserted is hardware dependent.
9 However, when asserted it may not be possible to access the hardware's
Dti,tps380x-reset.yaml16 reset input (MR). The RESET output remains asserted for the factory
/Documentation/devicetree/bindings/mmc/
Dmmc-pwrseq-simple.yaml26 contains a list of GPIO specifiers. The reset GPIOs are asserted
28 They will be de-asserted right after the power has been provided to the
Dmmc-pwrseq-emmc.yaml30 contains a GPIO specifier. The reset GPIO is asserted
/Documentation/hwmon/
Dadm9240.rst90 Temperature alarm is asserted once the temperature exceeds the high limit,
114 - low speed alarm will be asserted if fan speed is
127 - alarm will be asserted
161 An alarm is asserted for any voltage going below or above the set limits.
172 An alarm is asserted when the CI pin goes active high. The ADM9240
Dlm93.rst103 signals. I.e. when #P1_PROCHOT is asserted, the LM93 will automatically
124 which 1 indicates #VRD_HOT is asserted and 0 indicates it is negated. These
254 If the #PROCHOT or #VRDHOT signals are asserted while bound to a PWM output
298 vrdhot<n> 0 means negated, 1 means asserted
303 pwm_auto_prochot_ramp ramp time per step when #PROCHOT asserted
304 pwm_auto_vrdhot_ramp ramp time per step when #VRDHOT asserted
/Documentation/devicetree/bindings/input/
Dgpio-keys.yaml87 Specifies whether the key should wake the system when asserted, when
93 EV_ACT_ANY - both asserted and deasserted
94 EV_ACT_ASSERTED - asserted
/Documentation/devicetree/bindings/spi/
Dspi-peripheral-props.yaml50 asserted.
55 de-asserted.
60 de-asserted.
Dcdns,qspi-nor-peripheral-props.yaml25 outputs are de-asserted between transactions.
/Documentation/driver-api/
Dreset.rst88 That is, an assert causes the reset line to be asserted immediately, and a
100 will actually cause the reset line to be asserted.
103 The API only guarantees that the reset line can not be asserted as long as any
130 reset line is asserted.
/Documentation/devicetree/bindings/memory-controllers/
Dmvebu-devbus.txt64 DEV_OEn and DEV_CSn are asserted at the same cycle.
73 DEV_OEn and DEV_CSn are de-asserted at the same cycle
76 DEV_OEn is always de-asserted the next cycle after
/Documentation/devicetree/bindings/gnss/
Dgnss-common.yaml28 asserted. If this line is active low, the GPIO phandle should
/Documentation/devicetree/bindings/net/
Dmaxlinear,gpy2xx.yaml20 interrupt line asserted for a random amount of time even after the
/Documentation/firmware-guide/acpi/
Dlpit.rst31 residency, or system time spent with the SLP_S0# signal asserted.
/Documentation/devicetree/bindings/rtc/
Dmicrochip,mfps-rtc.yaml30 RTC_MATCH, asserted when the content of the Alarm register is equal

1234