Searched full:assigned (Results 1 – 25 of 486) sorted by relevance
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| /Documentation/devicetree/bindings/phy/ |
| D | mixel,mipi-dsi-phy.yaml | 65 - assigned-clocks
66 - assigned-clock-parents
67 - assigned-clock-rates
76 assigned-clocks: false
77 assigned-clock-parents: false
78 assigned-clock-rates: false
93 assigned-clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>;
94 assigned-clock-parents = <&clk IMX8MQ_VIDEO_PLL1_OUT>;
95 assigned-clock-rates = <24000000>;
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| D | ti,phy-j721e-wiz.yaml | 95 assigned-clocks:
98 assigned-clock-parents:
104 - assigned-clocks
105 - assigned-clock-parents
131 assigned-clocks:
134 assigned-clock-parents:
140 - assigned-clocks
141 - assigned-clock-parents
210 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
211 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
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| D | phy-rockchip-typec.txt | 11 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
13 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
46 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
47 assigned-clock-rates = <50000000>;
70 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
71 assigned-clock-rates = <50000000>;
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| /Documentation/devicetree/bindings/sound/ |
| D | brcm,cygnus-audio.txt | 13 - assigned-clocks: PLL and leaf clocks
14 - assigned-clock-parents: parent clocks of the assigned clocks
16 - assigned-clock-rates: List of clock frequencies of the
17 assigned clocks
36 assigned-clocks = <&audiopll BCM_CYGNUS_AUDIOPLL>,
40 assigned-clock-parents = <&audiopll BCM_CYGNUS_AUDIOPLL>;
41 assigned-clock-rates = <1769470191>,
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| D | nvidia,tegra-audio-graph-card.yaml | 35 assigned-clocks:
39 assigned-clock-parents:
43 assigned-clock-rates:
63 - assigned-clocks
64 - assigned-clock-parents
79 assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>,
82 assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
83 assigned-clock-rates = <368640000>, <49152000>, <12288000>;
101 assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
102 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
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| D | nvidia,tegra210-dmic.yaml | 45 assigned-clocks:
48 assigned-clock-parents:
51 assigned-clock-rates:
79 - assigned-clocks
80 - assigned-clock-parents
93 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
94 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
95 assigned-clock-rates = <3072000>;
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| D | nvidia,tegra186-dspk.yaml | 45 assigned-clocks:
48 assigned-clock-parents:
51 assigned-clock-rates:
79 - assigned-clocks
80 - assigned-clock-parents
94 assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>;
95 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
96 assigned-clock-rates = <12288000>;
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| D | nvidia,tegra210-ahub.yaml | 43 assigned-clocks:
46 assigned-clock-parents:
49 assigned-clock-rates:
122 - assigned-clocks
123 - assigned-clock-parents
139 assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
140 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
176 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>;
177 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
178 assigned-clock-rates = <1536000>;
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| D | nvidia,tegra210-i2s.yaml | 58 assigned-clocks:
62 assigned-clock-parents:
66 assigned-clock-rates:
95 - assigned-clocks
96 - assigned-clock-parents
109 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>;
110 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
111 assigned-clock-rates = <1536000>;
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| /Documentation/process/ |
| D | cve.rst | 8 regards to the kernel project, and CVE numbers were very often assigned
21 A list of all assigned CVEs for the Linux kernel can be found in the
24 assigned CVEs, please `subscribe
32 for CVE number assignments and have CVE numbers automatically assigned
45 should have a CVE assigned to it, please email them at <cve@kernel.org>
53 No CVEs will be automatically assigned for unfixed security issues in
57 have a CVE assigned before an issue is resolved with a commit, please
59 identifier assigned from their batch of reserved identifiers.
61 No CVEs will be assigned for any issue found in a version of the kernel
66 Disputes of assigned CVEs
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | nxp,imx8qxp-adc.yaml | 33 assigned-clocks:
36 assigned-clock-rates:
57 - assigned-clocks
58 - assigned-clock-rates
78 assigned-clocks = <&clk IMX_SC_R_ADC_0>;
79 assigned-clock-rates = <24000000>;
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | sony,imx334.yaml | 27 assigned-clocks: true
28 assigned-clock-parents: true
29 assigned-clock-rates: true
77 assigned-clocks = <&imx334_clk>;
78 assigned-clock-parents = <&imx334_clk_parent>;
79 assigned-clock-rates = <24000000>;
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| D | ovti,ov5648.yaml | 23 assigned-clocks:
26 assigned-clock-rates:
71 - assigned-clocks
72 - assigned-clock-rates
96 assigned-clocks = <&ov5648_xvclk 0>;
97 assigned-clock-rates = <24000000>;
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| D | sony,imx412.yaml | 29 assigned-clocks: true
30 assigned-clock-parents: true
31 assigned-clock-rates: true
89 assigned-clocks = <&imx412_clk>;
90 assigned-clock-parents = <&imx412_clk_parent>;
91 assigned-clock-rates = <24000000>;
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| D | ovti,ov8865.yaml | 23 assigned-clocks:
26 assigned-clock-rates:
71 - assigned-clocks
72 - assigned-clock-rates
97 assigned-clocks = <&ccu CLK_CSI_MCLK>;
98 assigned-clock-rates = <24000000>;
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| D | ovti,ov9282.yaml | 30 assigned-clocks: true
31 assigned-clock-parents: true
32 assigned-clock-rates: true
90 assigned-clocks = <&ov9282_clk>;
91 assigned-clock-parents = <&ov9282_clk_parent>;
92 assigned-clock-rates = <24000000>;
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| D | sony,imx335.yaml | 27 assigned-clocks: true
28 assigned-clock-parents: true
29 assigned-clock-rates: true
89 assigned-clocks = <&imx335_clk>;
90 assigned-clock-parents = <&imx335_clk_parent>;
91 assigned-clock-rates = <24000000>;
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| D | hynix,hi846.yaml | 31 assigned-clocks:
34 assigned-clock-rates:
85 - assigned-clocks
86 - assigned-clock-rates
108 assigned-clocks = <&clk 0>;
109 assigned-clock-rates = <25000000>;
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| /Documentation/devicetree/bindings/ufs/ |
| D | ti,j721e-ufs.yaml | 28 assigned-clocks:
31 assigned-clock-parents:
71 assigned-clocks = <&k3_clks 277 1>;
72 assigned-clock-parents = <&k3_clks 277 4>;
85 assigned-clocks = <&k3_clks 277 1>;
86 assigned-clock-parents = <&k3_clks 277 4>;
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| /Documentation/devicetree/bindings/media/ |
| D | mediatek,vcodec-encoder.yaml | 45 assigned-clocks: true
47 assigned-clock-parents: true
82 - assigned-clocks
83 - assigned-clock-parents
164 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
165 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
184 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
185 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;
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| /Documentation/devicetree/bindings/pwm/ |
| D | imx-tpm-pwm.yaml | 32 assigned-clocks:
35 assigned-clock-parents:
55 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
56 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
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| D | pwm-sprd.txt | 16 - assigned-clocks: Reference to the PWM clock entries.
17 - assigned-clock-parents: The phandle of the parent clock of PWM clock.
31 assigned-clocks = <&aon_clk CLK_PWM0>,
35 assigned-clock-parents = <&ext_26m>,
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| /Documentation/devicetree/bindings/display/hisilicon/ |
| D | hisi-ade.txt | 20 - assigned-clocks: Should contain "clk_ade_core" and "clk_codec_jpeg" clocks'
22 - assigned-clock-rates: clock rates, one for each entry in assigned-clocks.
54 assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
56 assigned-clock-rates = <360000000>, <288000000>;
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| /Documentation/devicetree/bindings/display/imx/ |
| D | nxp,imx8mq-dcss.yaml | 58 assigned-clocks:
65 assigned-clock-parents:
71 assigned-clock-rates:
96 assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>, <&clk IMX8MQ_CLK_DISP_RTRM>,
98 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, <&clk IMX8MQ_SYS1_PLL_800M>,
100 assigned-clock-rates = <800000000>,
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| /Documentation/devicetree/bindings/spmi/ |
| D | mtk,spmi-mtk-pmif.yaml | 48 assigned-clocks:
51 assigned-clock-parents:
78 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
79 assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
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