Searched +full:ast2600 +full:- +full:lpc +full:- +full:v2 (Results 1 – 3 of 3) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)4 ---5 $id: http://devicetree.org/schemas/mfd/aspeed-lpc.yaml#6 $schema: http://devicetree.org/meta-schemas/core.yaml#8 title: Aspeed Low Pin Count (LPC) Bus Controller11 - Andrew Jeffery <andrew@aj.id.au>12 - Chia-Wei Wang <chiawei_wang@aspeedtech.com>15 The LPC bus is a means to bridge a host CPU to a number of low-bandwidth17 primary use case of the Aspeed LPC controller is as a slave on the bus21 The LPC controller is represented as a multi-function device to account for the[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/ipmi/aspeed,ast2400-kcs-bmc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Andrew Jeffery <andrew@aj.id.au>13 The Aspeed BMC SoCs typically use the Keyboard-Controller-Style (KCS)14 interfaces on the LPC bus for in-band IPMI communication with their host.19 - description: Channel ID derived from reg22 - aspeed,ast2400-kcs-bmc-v223 - aspeed,ast2500-kcs-bmc-v2[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)5 ---6 $id: http://devicetree.org/schemas/soc/aspeed/uart-routing.yaml#7 $schema: http://devicetree.org/meta-schemas/core.yaml#12 - Oskar Senft <osk@google.com>13 - Chia-Wei Wang <chiawei_wang@aspeedtech.com>17 the built-in UARTS and physical serial I/O ports.20 This can be used to enable Host <-> BMC communication via UARTs, e.g. to30 - enum:31 - aspeed,ast2400-uart-routing[all …]