Searched full:bandwidth (Results 1 – 25 of 187) sorted by relevance
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| /Documentation/driver-api/cxl/ |
| D | access-coordinates.rst | 11 Root Ports (RP), there is the possibility of the total bandwidth for all
63 cxl_endpoint_gather_bandwidth() function. The min() of bandwidth from the
64 endpoint CDAT and the upstream link bandwidth is calculated. If the endpoint
65 has a CXL switch as a parent, then min() of calculated bandwidth and the
66 bandwidth from the SSLBIS for the switch downstream port that is associated
67 with the endpoint is calculated. The final bandwidth is stored in a
76 gathered bandwidth and the upstream link bandwidth. If there's a switch
84 The next step is to take the min() of the per host bridge bandwidth and the
85 bandwidth from the Generic Port (GP). The bandwidths for the GP is retrieved
86 via ACPI tables SRAT/HMAT. The min bandwidth are aggregated under the same
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| /Documentation/admin-guide/perf/ |
| D | hisi-pcie-pmu.rst | 6 bandwidth, latency, bus utilization and buffer occupancy data of PCIe.
45 The related events usually used to calculate the bandwidth, latency or others.
51 bandwidth events "xxx_flux, xxx_time".
93 "bdf" filter can only be used in bandwidth events, target Endpoint is
94 selected by configuring BDF to "bdf". Counter only counts the bandwidth of
108 only be used in bandwidth events.
122 "thr_mode". This filter can only be used in bandwidth events.
134 When counting bandwidth, the data can be composed of certain parts of TLP
138 - 2'b01: Bandwidth of TLP payloads
139 - 2'b10: Bandwidth of TLP headers
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| D | meson-ddr-pmu.rst | 4 Amlogic SoC DDR Bandwidth Performance Monitoring Unit (PMU)
7 The Amlogic Meson G12 SoC contains a bandwidth monitor inside DRAM controller.
10 to show if the performance bottleneck is on DDR bandwidth.
55 + Show the total DDR bandwidth per seconds:
62 + Show individual DDR bandwidth from CPU and GPU respectively, as well as
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| D | alibaba_pmu.rst | 30 - Group 1: PMU Bandwidth Counters. This group has 8 counters that are used
54 interface, we could calculate the bandwidth. Example usage of counting memory
55 data bandwidth::
91 Example usage of counting all memory read/write bandwidth by metric::
96 The average DRAM bandwidth can be calculated as follows:
98 - Read Bandwidth = perf_hif_rd * DDRC_WIDTH * DDRC_Freq / DDRC_Cycle
99 - Write Bandwidth = (perf_hif_wr + perf_hif_rmw) * DDRC_WIDTH * DDRC_Freq / DDRC_Cycle
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| D | dwc_pcie_pmu.rst | 80 The average RX/TX bandwidth can be calculated using the following formula:
82 PCIe RX Bandwidth = Rx_PCIe_TLP_Data_Payload / Measure_Time_Window
83 PCIe TX Bandwidth = Tx_PCIe_TLP_Data_Payload / Measure_Time_Window
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| /Documentation/scheduler/ |
| D | sched-bwc.rst | 2 CFS Bandwidth Control
6 This document only discusses CPU bandwidth control for SCHED_NORMAL.
9 CFS bandwidth control is a CONFIG_FAIR_GROUP_SCHED extension which allows the
10 specification of the maximum CPU bandwidth available to a group or hierarchy.
12 The bandwidth allowed for a group is specified using a quota and period. Within
21 cfs_quota units at each period boundary. As threads consume this bandwidth it
30 Traditional (UP-EDF) bandwidth control is something like:
89 bandwidth restriction in place, such a group is described as an unconstrained
90 bandwidth group. This represents the traditional work-conserving behavior for
94 enact the specified bandwidth limit. The minimum quota allowed for the quota or
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| D | sched-rt-group.rst | 43 the amount of bandwidth (eg. CPU time) being constant. In order to schedule
90 The scheduling period that is equivalent to 100% CPU bandwidth.
97 CONFIG_RT_GROUP_SCHED=y it signifies the total bandwidth available to all
116 By default all bandwidth is assigned to the root group and new groups get the
118 want to assign bandwidth to another group, reduce the root group's bandwidth
122 bandwidth to the group before it will accept real-time tasks. Therefore you will
132 CPU bandwidth to task groups.
160 Consider two sibling groups A and B; both have 50% bandwidth, but A's
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| D | sched-deadline.rst | 11 2.2 Bandwidth reclaiming
17 4. Bandwidth management
42 algorithm, augmented with a mechanism (called Constant Bandwidth Server, CBS)
62 "admission control" strategy (see Section "4. Bandwidth management") is used
67 interference between different tasks (bandwidth isolation), while the EDF[1]
125 2.2 Bandwidth reclaiming
128 Bandwidth reclaiming for deadline tasks is based on the GRUB (Greedy
129 Reclamation of Unused Bandwidth) algorithm [15, 16, 17] and it is enabled
164 bandwidth cannot be immediately reclaimed without breaking the
167 the 0-lag time, when the task's bandwidth can be reclaimed without
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| /Documentation/ABI/removed/ |
| D | sysfs-kernel-uids | 7 to set the cpu bandwidth a user is allowed. This is a
10 shares, then they will get equal CPU bandwidth. Another
13 bandwidth user A will. For more details refer
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| /Documentation/devicetree/bindings/net/ |
| D | microchip,sparx5-switch.yaml | 100 microchip,bandwidth:
101 description: Specifies bandwidth in Mbit/s allocated to the port.
118 - microchip,bandwidth
156 microchip,bandwidth = <1000>;
165 microchip,bandwidth = <25000>;
174 microchip,bandwidth = <25000>;
183 microchip,bandwidth = <25000>;
192 microchip,bandwidth = <25000>;
202 microchip,bandwidth = <1000>;
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| /Documentation/arch/x86/ |
| D | resctrl.rst | 25 MBM (Memory Bandwidth Monitoring) "cqm_mbm_total", "cqm_mbm_local"
26 MBA (Memory Bandwidth Allocation) "mba"
27 SMBA (Slow Memory Bandwidth Allocation) ""
28 BMEC (Bandwidth Monitoring Event Configuration) ""
48 bandwidth in MiBps
138 Memory bandwidth(MB) subdirectory contains the following files
142 The minimum memory bandwidth percentage which
146 The granularity in which the memory bandwidth
150 available bandwidth control steps are:
161 request different memory bandwidth percentages:
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| /Documentation/devicetree/bindings/perf/ |
| D | amlogic,g12-ddr-pmu.yaml | 13 Amlogic G12 series SoC integrate DDR bandwidth monitor.
15 The bandwidth is counted in the timer ISR. Different platform
27 - description: DMC bandwidth register space.
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| /Documentation/devicetree/bindings/interconnect/ |
| D | qcom,msm8998-bwmon.yaml | 7 title: Qualcomm Interconnect Bandwidth Monitor
13 Bandwidth Monitor measures current throughput on buses between various NoC
16 Certain SoCs might have more than one Bandwidth Monitors, for example on SDM845::
17 - Measuring the bandwidth between CPUs and Last Level Cache Controller -
19 - Measuring the bandwidth between Last Level Cache Controller and memory
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| D | qcom,osm-l3.yaml | 13 L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM.
14 The OSM L3 interconnect provider aggregates the L3 bandwidth requests
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| /Documentation/userspace-api/media/dvb/ |
| D | fe-bandwidth-t.rst | 4 Frontend bandwidth
26 - Autodetect bandwidth (if supported)
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| D | frontend-property-terrestrial-systems.rst | 29 - :ref:`DTV_BANDWIDTH_HZ <DTV-BANDWIDTH-HZ>`
71 - :ref:`DTV_BANDWIDTH_HZ <DTV-BANDWIDTH-HZ>`
134 - :ref:`DTV_BANDWIDTH_HZ <DTV-BANDWIDTH-HZ>`
201 - :ref:`DTV_BANDWIDTH_HZ <DTV-BANDWIDTH-HZ>`
224 - :ref:`DTV_BANDWIDTH_HZ <DTV-BANDWIDTH-HZ>`
279 - :ref:`DTV_BANDWIDTH_HZ <DTV-BANDWIDTH-HZ>`
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| /Documentation/devicetree/bindings/display/ti/ |
| D | ti,k2g-dss.yaml | 61 max-memory-bandwidth:
64 Input memory (from main memory to dispc) bandwidth limit in
98 max-memory-bandwidth = <230000000>;
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| D | ti,omap2-dss.txt | 32 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
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| D | ti,dra7-dss.txt | 51 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
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| D | ti,omap3-dss.txt | 41 - max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
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| /Documentation/ABI/testing/ |
| D | sysfs-module | 25 However there are cases, when 80% max isochronous bandwidth is
27 microseconds of isochronous bandwidth per microframe to work
32 microseconds of periodic bandwidth per microframe.
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| /Documentation/block/ |
| D | bfq-iosched.rst | 12 - BFQ distributes bandwidth, not just time, among processes or
126 Strong fairness, bandwidth and delay guarantees
131 workload and regardless of the device parameters. From these bandwidth
291 bandwidth is distributed in proportion to the weight of each
292 queue. A very thin extra bandwidth is however guaranteed to
400 receives its allotted share of the bandwidth. The first condition is
450 DISABLE this mode if you need full control on bandwidth
452 increases the bandwidth share of privileged applications, as the main
470 short-term bandwidth and latency guarantees, especially if the
481 values is that they coarsen the granularity of short-term bandwidth
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| /Documentation/userspace-api/media/v4l/ |
| D | ext-ctrls-rf-tuner.rst | 39 Enables/disables tuner radio channel bandwidth configuration. In
40 automatic mode bandwidth configuration is performed by the driver.
45 desired bandwidth requirement. Used when
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| /Documentation/mm/ |
| D | numa.rst | 30 Memory access time and effective memory bandwidth varies depending on how far
39 memory bandwidth. However, to achieve scalable memory bandwidth, system and
52 faster access times and higher effective bandwidth than accesses to more
59 a given node will see the same local memory access times and bandwidth.
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| /Documentation/devicetree/bindings/net/wireless/ |
| D | mediatek,mt76.yaml | 189 rates for multiple channel bandwidth settings.
190 Each set starts with the number of channel bandwidth
193 channel bandwidth settings is 20, 40, 80 and 160 MHz.
203 for multiple channel bandwidth or resource unit settings.
204 Each set starts with the number of channel bandwidth or
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