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/Documentation/devicetree/bindings/pinctrl/
Dpinctrl-st.txt3 Each multi-function pin is controlled, driven and routed through the
5 and multiple alternate functions(ALT1 - ALTx) that directly connect
14 GPIO bank can have one of the two possible types of interrupt-wirings.
17 reduces number of overall interrupts numbers required. All these banks belong to
20 | |----> [gpio-bank (n) ]
21 | |----> [gpio-bank (n + 1)]
22 [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23 | |----> [gpio-bank (... )]
24 |_________|----> [gpio-bank (n + 7)]
26 Second type has a dedicated interrupt per gpio bank.
[all …]
Dmicrochip,sparx5-sgpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
14 the number of available GPIOs with a minimum number of additional
21 pattern: "^gpio@[0-9a-f]+$"
25 - microchip,sparx5-sgpio
26 - mscc,ocelot-sgpio
27 - mscc,luton-sgpio
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Dsamsung,pinctrl-gpio-bank.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/samsung,pinctrl-gpio-bank.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung S3C/S5P/Exynos SoC pin controller - gpio bank
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
12 - Tomasz Figa <tomasz.figa@gmail.com>
18 GPIO bank description for Samsung S3C/S5P/Exynos SoC pin controller.
24 '#gpio-cells':
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Dallwinner,sun4i-a10-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/allwinner,sun4i-a10-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#gpio-cells":
17 GPIO consumers must use three arguments, first the number of the
18 bank, then the pin number inside that bank, and finally the GPIO
21 "#interrupt-cells":
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Dpinctrl-sirf.txt4 - compatible : "sirf,prima2-pinctrl"
5 - reg : Address range of the pinctrl registers
6 - interrupts : Interrupts used by every GPIO group
7 - gpio-controller : Indicates this device is a GPIO controller
8 - interrupt-controller : Marks the device node as an interrupt controller
10 - sirf,pullups : if n-th bit of m-th bank is set, set a pullup on GPIO-n of bank m
11 - sirf,pulldowns : if n-th bit of m-th bank is set, set a pulldown on GPIO-n of bank m
13 Please refer to pinctrl-bindings.txt in this directory for details of the common
16 SiRFprimaII's pinmux nodes act as a container for an arbitrary number of subnodes.
19 Required subnode-properties:
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Dst,stm32-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre TORGUE <alexandre.torgue@foss.st.com>
17 on-chip controllers onto these pads.
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
24 - st,stm32f746-pinctrl
25 - st,stm32f769-pinctrl
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Datmel,at91rm9200-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/atmel,at91rm9200-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Manikandan Muralidharan <manikandan.m@microchip.com>
22 - items:
23 - enum:
24 - atmel,at91rm9200-pinctrl
25 - atmel,at91sam9x5-pinctrl
26 - atmel,sama5d3-pinctrl
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Dsamsung,pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
12 - Tomasz Figa <tomasz.figa@gmail.com>
19 the following format 'pinctrl{n}' where n is a unique number for the alias.
22 - External GPIO interrupts (see interrupts property in pin controller node);
24 - External wake-up interrupts - multiplexed (capable of waking up the system
25 see interrupts property in external wake-up interrupt controller node -
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Dpinctrl-mcp23s08.txt2 8-/16-bit I/O expander with serial interface (I2C/SPI)
5 - compatible : Should be
6 - "mcp,mcp23s08" (DEPRECATED) for 8 GPIO SPI version
7 - "mcp,mcp23s17" (DEPRECATED) for 16 GPIO SPI version
8 - "mcp,mcp23008" (DEPRECATED) for 8 GPIO I2C version or
9 - "mcp,mcp23017" (DEPRECATED) for 16 GPIO I2C version of the chip
11 - "microchip,mcp23s08" for 8 GPIO SPI version
12 - "microchip,mcp23s17" for 16 GPIO SPI version
13 - "microchip,mcp23s18" for 16 GPIO SPI version
14 - "microchip,mcp23008" for 8 GPIO I2C version or
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/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
Dgpio.txt1 Every GPIO controller node must have #gpio-cells property defined,
2 this information will be used to translate gpio-specifiers.
10 - compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b",
11 "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d",
12 "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank"
13 - #gpio-cells : Should be two. The first cell is the pin number and the
15 - gpio-controller : Marks the port as GPIO controller.
17 - fsl,cpm1-gpio-irq-mask : For banks having interrupt capability (like port C
20 - interrupts : This property provides the list of interrupt for each GPIO having
21 one as described by the fsl,cpm1-gpio-irq-mask property. There should be as
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/Documentation/devicetree/bindings/firmware/
Dcznic,turris-omnia-mcu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/cznic,turris-omnia-mcu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Behún <kabel@kernel.org>
18 const: cznic,turris-omnia-mcu
27 interrupt-controller: true
29 '#interrupt-cells':
32 The first cell specifies the interrupt number (0 to 63), the second cell
37 IRQ number GPIO bank GPIO pin within bank
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/Documentation/devicetree/bindings/gpio/
Dbrcm,brcmstb-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The controller's registers are organized as sets of eight 32-bit
11 registers with each set controlling a bank of up to 32 pins. A single
15 - Doug Berger <opendmb@gmail.com>
16 - Florian Fainelli <f.fainelli@gmail.com>
21 - enum:
22 - brcm,bcm7445-gpio
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Dmicrochip,pic32-gpio.txt4 - compatible: "microchip,pic32mzda-gpio"
5 - reg: Base address and length for the device.
6 - interrupts: The port interrupt shared by all pins.
7 - gpio-controller: Marks the port as GPIO controller.
8 - #gpio-cells: Two. The first cell is the pin number and
10 defined in <dt-bindings/gpio/gpio.h>:
14 - interrupt-controller: Marks the device node as an interrupt controller.
15 - #interrupt-cells: Two. The first cell is the GPIO number and second cell
17 <dt-bindings/interrupt-controller/irq.h>:
21 - clocks: Clock specifier (see clock bindings for details).
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Dbrcm,kona-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/brcm,kona-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 support up to 8 banks of 32 GPIOs where each bank has its own IRQ. The
15 - Ray Jui <rjui@broadcom.com>
20 - enum:
21 - brcm,bcm11351-gpio
22 - brcm,bcm21664-gpio
23 - brcm,bcm23550-gpio
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Dgpio.txt5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
24 and bit-banged data signals:
27 gpio-controller;
28 #gpio-cells = <2>;
32 data-gpios = <&gpio1 12 0>,
44 recommended to use the two-cell approach.
48 include/dt-bindings/gpio/gpio.h whenever possible:
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Dnxp,lpc3220-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/nxp,lpc3220-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Animesh Agarwal <animeshagarwal28@gmail.com>
14 const: nxp,lpc3220-gpio
19 gpio-controller: true
21 '#gpio-cells':
24 1) bank:
31 2) pin number
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/Documentation/devicetree/bindings/mtd/
Dfsmc-nand.txt5 - compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand"
6 - reg : Address range of the mtd chip
7 - reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd"
10 - bank-width : Width (in bytes) of the device. If not present, the width
12 - nand-skip-bbtscan: Indicates the BBT scanning should be skipped
13 - timings: array of 6 bytes for NAND timings. The meanings of these bytes
15 byte 0 TCLR : CLE to RE delay in number of AHB clock cycles, only 4 bits
19 byte 2 THIZ : number of HCLK clock cycles during which the data bus is
20 kept in Hi-Z (tristate) after the start of a write access.
23 byte 3 THOLD : number of HCLK clock cycles to hold the address (and data
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Dingenic,nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: nand-controller.yaml#
14 - $ref: /schemas/memory-controllers/ingenic,nemc-peripherals.yaml#
19 - ingenic,jz4740-nand
20 - ingenic,jz4725b-nand
21 - ingenic,jz4780-nand
25 - description: Bank number, offset and size of first attached NAND chip
[all …]
Dorion-nand.txt4 - compatible : "marvell,orion-nand".
5 - reg : Base physical address of the NAND and length of memory mapped
9 - cle : Address line number connected to CLE. Default is 0
10 - ale : Address line number connected to ALE. Default is 1
11 - bank-width : Width in bytes of the device. Default is 1
12 - chip-delay : Chip dependent delay for transferring data from array to read
15 The device tree may optionally contain sub-nodes describing partitions of the
21 #address-cells = <1>;
22 #size-cells = <1>;
25 bank-width = <1>;
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/Documentation/hwmon/
Dabituguru-datasheet.rst14 Olle Sandberg <ollebull@gmail.com>, 2005-05-25
27 Hans de Goede <j.w.r.degoede@hhs.nl>, 28-01-2006
33 As far as known the uGuru is always placed at and using the (ISA) I/O-ports
34 0xE0 and 0xE4, so we don't have to scan any port-range, just check what the two
35 ports are holding for detection. We will refer to 0xE0 as CMD (command-port)
39 present. We have to check for two different values at data-port, because
41 later on attached again data-port will hold 0x08, more about this later.
57 ----------
59 The uGuru has a number of different addressing levels. The first addressing
60 level we will call banks. A bank holds data for one or more sensors. The data
[all …]
/Documentation/devicetree/bindings/memory-controllers/
Dexynos-srom.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
19 - const: samsung,exynos4210-srom
24 "#address-cells":
27 "#size-cells":
34 Reflects the memory layout with four integer values per bank. Format:
35 <bank-number> 0 <parent address of bank> <size>
[all …]
Dmc-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/mc-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a Memory Controller bus.
13 to be defined in the peripheral node because they are per-peripheral
20 - Marek Vasut <marex@denx.de>
24 description: Bank number, base address and size of the device.
26 bank-width:
28 description: Bank width of the device, in bytes.
[all …]
/Documentation/devicetree/bindings/interrupt-controller/
Dbrcm,bcm2835-armctrl-ic.txt1 BCM2835 Top-Level ("ARMCTRL") Interrupt Controller
3 The BCM2835 contains a custom top-level interrupt controller, which supports
4 72 interrupt sources using a 2-level register scheme. The interrupt
9 interrupts, but the per-CPU interrupt controller is the root, and an
14 - compatible : should be "brcm,bcm2835-armctrl-ic" or
15 "brcm,bcm2836-armctrl-ic"
16 - reg : Specifies base physical address and size of the registers.
17 - interrupt-controller : Identifies the node as an interrupt controller
18 - #interrupt-cells : Specifies the number of cells needed to encode an
21 The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic
[all …]
/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/
Dpar_io.txt10 - device_type : should be "par_io".
11 - reg : offset to the register set and its length.
12 - num-ports : number of Parallel I/O ports
17 #address-cells = <1>;
18 #size-cells = <0>;
20 num-ports = <7>;
26 the new device trees. Instead, each Par I/O bank should be represented
27 via its own gpio-controller node:
30 - #gpio-cells : should be "2".
31 - compatible : should be "fsl,<chip>-qe-pario-bank",
[all …]
/Documentation/devicetree/bindings/bus/
Dsocionext,uniphier-system-bus.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/bus/socionext,uniphier-system-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The UniPhier System Bus is an external bus that connects on-board devices to
11 the UniPhier SoC. It is a simple (semi-)parallel bus with address, data, and
16 within each bank to the CPU-viewed address. The needed setup includes the
17 base address, the size of each bank. Optionally, some timing parameters can
21 - Masahiro Yamada <yamada.masahiro@socionext.com>
25 const: socionext,uniphier-system-bus
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