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/Documentation/netlink/specs/
Dnftables.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
4 protocol: netlink-raw
11 -
15 -
16 name: nfgen-family
18 -
21 -
22 name: res-id
23 byte-order: big-endian
25 -
[all …]
Dovs_flow.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
5 protocol: genetlink-legacy
6 uapi-header: linux/openvswitch.h
12 -
13 name: ovs-header
18 -
19 name: dp-ifindex
24 -
25 name: ovs-flow-stats
28 -
[all …]
Dnfsd.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
5 uapi-header: linux/nfsd_netlink.h
9 attribute-sets:
10 -
11 name: rpc-status
13 -
16 byte-order: big-endian
17 -
20 -
23 -
[all …]
Dtc.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
4 protocol: netlink-raw
12 -
16 -
19 -
23 -
26 -
29 -
32 -
35 -
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Dtcp_metrics.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
5 protocol: genetlink-legacy
10 c-family-name: tcp-metrics-genl-name
11 c-version-name: tcp-metrics-genl-version
12 max-by-define: true
13 kernel-policy: global
16 -
17 name: tcp-fastopen-cookie-max
21 attribute-sets:
22 -
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Dfou.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
5 protocol: genetlink-legacy
8 Foo-over-UDP.
10 c-family-name: fou-genl-name
11 c-version-name: fou-genl-version
12 max-by-define: true
13 kernel-policy: global
16 -
19 name-prefix: fou-encap-
20 enum-name:
[all …]
Dmptcp_pm.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
4 protocol: genetlink-legacy
7 c-family-name: mptcp-pm-name
8 c-version-name: mptcp-pm-ver
9 max-by-define: true
10 kernel-policy: per-op
11 cmd-cnt-name: --mptcp-pm-cmd-after-last
14 -
16 name: event-type
17 enum-name: mptcp-event-type
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/Documentation/devicetree/bindings/regmap/
Dregmap.txt5 little-endian,
6 big-endian,
7 native-endian: See common-properties.txt for a definition
10 Regmap defaults to little-endian register access on MMIO based
12 architectures that typically run big-endian operating systems
13 (e.g. PowerPC), registers can be defined as big-endian and must
16 On SoCs that can be operated in both big-endian and little-endian
19 chips), "native-endian" is used to allow using the same device tree
23 Scenario 1 : a register set in big-endian mode.
27 big-endian;
/Documentation/devicetree/bindings/phy/
Dlantiq,vrx200-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
13 "#phy-cells":
15 description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h>
19 - lantiq,vrx200-pcie-phy
20 - lantiq,arx300-pcie-phy
27 - description: PHY module clock
[all …]
/Documentation/devicetree/bindings/
Dcommon-properties.txt5 ----------
13 - big-endian: Boolean; force big endian register accesses
15 know the peripheral always needs to be accessed in big endian (BE) mode.
16 - little-endian: Boolean; force little endian register accesses
18 peripheral always needs to be accessed in little endian (LE) mode.
19 - native-endian: Boolean; always use register accesses matched to the
20 endianness of the kernel binary (e.g. LE vmlinux -> readl/writel,
21 BE vmlinux -> ioread32be/iowrite32be). In this case no byte swaps
22 will ever be performed. Use this if the hardware "self-adjusts"
27 In such cases, little-endian is the preferred default, but it is not
[all …]
/Documentation/devicetree/bindings/counter/
Dftm-quaddec.txt6 - compatible: Must be "fsl,ftm-quaddec".
7 - reg: Must be set to the memory region of the flextimer.
10 - big-endian: Access the device registers in big-endian mode.
14 compatible = "fsl,ftm-quaddec";
16 big-endian;
/Documentation/devicetree/bindings/usb/
Dgeneric-ehci.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/generic-ehci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
13 - $ref: usb-hcd.yaml
14 - if:
19 const: ibm,usb-ehci-440epx
28 - items:
29 - enum:
[all …]
Dgeneric-ohci.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/generic-ohci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
15 - items:
16 - enum:
17 - allwinner,sun4i-a10-ohci
18 - allwinner,sun50i-a64-ohci
19 - allwinner,sun50i-h6-ohci
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/Documentation/devicetree/bindings/i2c/
Di2c-mux-reg.txt1 Register-based I2C Bus Mux
7 - compatible: i2c-mux-reg
8 - i2c-parent: The phandle of the I2C bus that this multiplexer's master-side
10 * Standard I2C mux properties. See i2c-mux.yaml in this directory.
11 * I2C child bus nodes. See i2c-mux.yaml in this directory.
14 - reg: this pair of <offset size> specifies the register to control the mux.
15 The <offset size> depends on its parent node. It can be any memory-mapped
18 - little-endian: The existence indicates the register is in little endian.
19 - big-endian: The existence indicates the register is in big endian.
20 If both little-endian and big-endian are omitted, the endianness of the
[all …]
/Documentation/devicetree/bindings/display/
Dsm501fb.txt7 - compatible : should be "smi,sm501".
8 - reg : contain two entries:
9 - First entry: System Configuration register
10 - Second entry: IO space (Display Controller register)
11 - interrupts : SMI interrupt to the cpu should be described here.
14 - mode : select a video mode:
15 <xres>x<yres>[-<bpp>][@<refresh>]
16 - edid : verbatim EDID data block describing attached display.
19 - little-endian: available on big endian systems, to
20 set different foreign endian.
[all …]
Dfsl,dcu.txt4 - compatible: Should be one of
5 * "fsl,ls1021a-dcu".
6 * "fsl,vf610-dcu".
8 - reg: Address and length of the register set for dcu.
9 - clocks: Handle to "dcu" and "pix" clock (in the order below)
11 See ../clocks/clock-bindings.txt for details.
12 - clock-names: Should be "dcu" and "pix"
13 See ../clocks/clock-bindings.txt for details.
14 - big-endian Boolean property, LS1021A DCU registers are big-endian.
15 - port Video port for the panel output
[all …]
/Documentation/devicetree/bindings/sound/
Dfsl,spdif.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
20 - fsl,imx35-spdif
21 - fsl,vf610-spdif
22 - fsl,imx6sx-spdif
23 - fsl,imx8qm-spdif
24 - fsl,imx8qxp-spdif
25 - fsl,imx8mq-spdif
[all …]
Dfsl,esai.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
11 - Frank Li <Frank.Li@nxp.com>
14 The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial port
22 - fsl,imx35-esai
23 - fsl,imx6ull-esai
24 - fsl,imx8qm-esai
25 - fsl,vf610-esai
[all …]
/Documentation/devicetree/bindings/pwm/
Dfsl,vf610-ftm-pwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/fsl,vf610-ftm-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 SoC | FTM-PWM endianness
16 --------+-------------------
21 Please see ../regmap/regmap.txt for more detail about how to specify endian
25 - Frank Li <Frank.Li@nxp.com>
30 - fsl,vf610-ftm-pwm
31 - fsl,imx8qm-ftm-pwm
[all …]
/Documentation/devicetree/bindings/rtc/
Dfsl,ls-ftm-alarm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/fsl,ls-ftm-alarm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
15 - fsl,ls1012a-ftm-alarm
16 - fsl,ls1021a-ftm-alarm
17 - fsl,ls1028a-ftm-alarm
18 - fsl,ls1043a-ftm-alarm
19 - fsl,ls1046a-ftm-alarm
[all …]
/Documentation/devicetree/bindings/power/
Dbrcm,bcm-pmb.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/power/brcm,bcm-pmb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 - Rafał Miłecki <rafal@milecki.pl>
18 - brcm,bcm4908-pmb
19 - brcm,bcm63138-pmb
25 big-endian:
27 description: Flag to use for block working in big endian mode.
29 "#power-domain-cells":
[all …]
/Documentation/devicetree/bindings/mips/cavium/
Ductl.txt4 - compatible: "cavium,octeon-6335-uctl"
8 - reg: The base address of the UCTL register bank.
10 - #address-cells: Must be <2>.
12 - #size-cells: Must be <2>.
14 - ranges: Empty to signify direct mapping of the children.
16 - refclk-frequency: A single cell containing the reference clock
19 - refclk-type: A string describing the reference clock connection
24 compatible = "cavium,octeon-6335-uctl";
27 #address-cells = <2>;
28 #size-cells = <2>;
[all …]
/Documentation/networking/device_drivers/cellular/qualcomm/
Drmnet.rst1 .. SPDX-License-Identifier: GPL-2.0
24 sending aggregated bunch of MAP frames. rmnet driver will de-aggregate
32 MAP header fields are in big endian format.
36 Bit 0 1 2-7 8-15 16-31
39 Bit 32-x
58 MAP header fields are in big endian format.
62 Bit 0 1 2-7 8-15 16-31
65 Bit 32-(x-33) (x-32)-x
83 by the hardware.Checksum offload header fields are in big endian format.
87 Bit 0-14 15 16-31
[all …]
/Documentation/devicetree/bindings/timer/
Dfsl,ftm-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/fsl,ftm-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Animesh Agarwal <animeshagarwal28@gmail.com>
14 const: fsl,ftm-timer
24 contain an entry for each entry in clock-names.
28 clock-names:
30 - const: ftm-evt
31 - const: ftm-src
[all …]
/Documentation/devicetree/bindings/dma/
Dfsl-qdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/fsl-qdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
15 - const: fsl,ls1021a-qdma
16 - items:
17 - enum:
18 - fsl,ls1028a-qdma
19 - fsl,ls1043a-qdma
[all …]

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