| /Documentation/devicetree/bindings/timer/ |
| D | renesas,cmt.yaml | 14 The CMT is a multi-channel 16/32/48-bit timer/counter with configurable clock
28 - renesas,r8a7740-cmt0 # 32-bit CMT0 on R-Mobile A1
29 - renesas,r8a7740-cmt1 # 48-bit CMT1 on R-Mobile A1
30 - renesas,r8a7740-cmt2 # 32-bit CMT2 on R-Mobile A1
31 - renesas,r8a7740-cmt3 # 32-bit CMT3 on R-Mobile A1
32 - renesas,r8a7740-cmt4 # 32-bit CMT4 on R-Mobile A1
33 - renesas,sh73a0-cmt0 # 32-bit CMT0 on SH-Mobile AG5
34 - renesas,sh73a0-cmt1 # 48-bit CMT1 on SH-Mobile AG5
35 - renesas,sh73a0-cmt2 # 32-bit CMT2 on SH-Mobile AG5
36 - renesas,sh73a0-cmt3 # 32-bit CMT3 on SH-Mobile AG5
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| /Documentation/devicetree/bindings/mfd/ |
| D | mc13xxx.txt | 55 sw1a : regulator SW1A (register 24, bit 0)
56 sw1b : regulator SW1B (register 25, bit 0)
57 sw2a : regulator SW2A (register 26, bit 0)
58 sw2b : regulator SW2B (register 27, bit 0)
59 sw3 : regulator SW3 (register 29, bit 20)
60 vaudio : regulator VAUDIO (register 32, bit 0)
61 viohi : regulator VIOHI (register 32, bit 3)
62 violo : regulator VIOLO (register 32, bit 6)
63 vdig : regulator VDIG (register 32, bit 9)
64 vgen : regulator VGEN (register 32, bit 12)
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| /Documentation/arch/arm64/ |
| D | asymmetric-32bit.rst | 2 Asymmetric 32-bit SoCs
7 This document describes the impact of asymmetric 32-bit SoCs on the
8 execution of 32-bit (``AArch32``) applications.
16 of the CPUs are capable of executing 32-bit user applications. On such
19 ``execve(2)`` of 32-bit ELF binaries, with the latter returning
21 64-bit-only CPU, then the onlining operation fails and the new CPU is
25 running legacy 32-bit binaries. Unsurprisingly, that doesn't work very
28 It seems inevitable that future SoCs will drop 32-bit support
30 run 32-bit code on one of these transitionary platforms then you would
38 allowing 32-bit tasks to run on an asymmetric 32-bit system requires an
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| D | booting.rst | 106 - The flags field (introduced in v3.17) is a little-endian 64-bit field
110 Bit 0 Kernel endianness. 1 if BE, 0 if LE.
111 Bit 1-2 Kernel Page size.
117 Bit 3 Kernel physical placement
126 the 48-bit addressable range of physical memory
194 kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0) set where
221 - SCR_EL3.HCE (bit 8) must be initialised to 0b1.
226 - ICC_SRE_EL3.Enable (bit 3) must be initialised to 0b1.
227 - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
228 - ICC_CTLR_EL3.PMHE (bit 6) must be set to the same value across
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| /Documentation/devicetree/bindings/crypto/ |
| D | fsl-sec2.txt | 16 (EUs) are available. It's a single 32-bit cell. EU information
20 bit 0 = reserved - should be 0
21 bit 1 = set if SEC has the ARC4 EU (AFEU)
22 bit 2 = set if SEC has the DES/3DES EU (DEU)
23 bit 3 = set if SEC has the message digest EU (MDEU/MDEU-A)
24 bit 4 = set if SEC has the random number generator EU (RNG)
25 bit 5 = set if SEC has the public key EU (PKEU)
26 bit 6 = set if SEC has the AES EU (AESU)
27 bit 7 = set if SEC has the Kasumi EU (KEU)
28 bit 8 = set if SEC has the CRC EU (CRCU)
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| /Documentation/ABI/testing/ |
| D | sysfs-driver-zynqmp-fpga | 7 of the FPGA device. Each bit position in the status value is
12 BIT(0) 0: No CRC error
15 BIT(1) 0: Decryptor security not set
18 BIT(2) 0: MMCMs/PLLs are not locked
21 BIT(3) 0: DCI not matched
24 BIT(4) 0: Start-up sequence has not finished
27 BIT(5) 0: All I/Os are placed in High-Z state
30 BIT(6) 0: Flip-flops and block RAM are write disabled
33 BIT(7) 0: GHIGH_B_STATUS asserted
36 BIT(8) to BIT(10) Status of the mode pins
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| D | sysfs-driver-jz4780-efuse | 10 0x000 64 bit Random Number
11 0x008 128 bit Ingenic Chip ID
12 0x018 128 bit Customer ID
13 0x028 3520 bit Reserved
14 0x1E0 8 bit Protect Segment
15 0x1E1 2296 bit HDMI Key
16 0x300 2048 bit Security boot key
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| /Documentation/i2c/ |
| D | ten-bit-addresses.rst | 2 I2C Ten-bit Addresses
5 The I2C protocol knows about two kinds of device addresses: normal 7 bit
6 addresses, and an extended set of 10 bit addresses. The sets of addresses
7 do not intersect: the 7 bit address 0x10 is not the same as the 10 bit
9 To avoid ambiguity, the user sees 10 bit addresses mapped to a different
11 10 bit mode. This is used for creating device names in sysfs. It is also
12 needed when instantiating 10 bit devices via the new_device file in sysfs.
14 I2C messages to and from 10-bit address devices have a different format.
17 The current 10 bit address support is minimal. It should work, however
20 * Not all bus drivers support 10-bit addresses. Some don't because the
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| /Documentation/devicetree/bindings/powerpc/ |
| D | ibm,powerpc-cpu-features.txt | 96 Value type: <u32> bit mask
98 Bit numbers are LSB0
99 bit 0 - PR (problem state / user mode)
100 bit 1 - OS (privileged state)
101 bit 2 - HV (hypervisor state)
107 If bit 0 is set, then the hwcap-bit-nr property will exist.
112 Value type: <u32> bit mask
114 Bit numbers are LSB0
115 bit 0 - HFSCR
125 If the HFSCR bit is set, then the hfscr-bit-nr property will exist and
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| /Documentation/userspace-api/media/cec/ |
| D | cec-pin-error-inj.rst | 46 # <op>[,<mode>] rx-low-drive <bit> force a low-drive condition at this bit position
58 # <op>[,<mode>] tx-no-eom don't set the EOM bit
59 # <op>[,<mode>] tx-early-eom set the EOM bit one byte too soon
62 # <op>[,<mode>] tx-short-bit <bit> make this bit shorter than allowed
63 # <op>[,<mode>] tx-long-bit <bit> make this bit longer than allowed
64 # <op>[,<mode>] tx-custom-bit <bit> send the custom pulse instead of this bit
68 # <op>[,<mode>] tx-last-bit <bit> stop sending after this bit
69 # <op>[,<mode>] tx-low-drive <bit> force a low-drive condition at this bit position
73 # <bit> CEC message bit (0-159)
74 # 10 bits per 'byte': bits 0-7: data, bit 8: EOM, bit 9: ACK
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-74xx-mmio.txt | 5 "ti,741g125": for 741G125 (1-bit Input),
6 "ti,741g174": for 741G74 (1-bit Output),
7 "ti,742g125": for 742G125 (2-bit Input),
8 "ti,7474" : for 7474 (2-bit Output),
9 "ti,74125" : for 74125 (4-bit Input),
10 "ti,74175" : for 74175 (4-bit Output),
11 "ti,74365" : for 74365 (6-bit Input),
12 "ti,74174" : for 74174 (6-bit Output),
13 "ti,74244" : for 74244 (8-bit Input),
14 "ti,74273" : for 74273 (8-bit Output),
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| /Documentation/admin-guide/ |
| D | highuid.rst | 2 Notes on the change from 16-bit UIDs to 32-bit UIDs
15 What's left to be done for 32-bit UIDs on all Linux architectures:
22 properly with huge UIDs. If it can deal with 64-bit file offsets on all
27 (currently, the old 16-bit UID and GID are still written to disk, and
28 part of the former pad space is used to store separate 32-bit UID and
31 - Need to validate that OS emulation calls the 16-bit UID
32 compatibility syscalls, if the OS being emulated used 16-bit UIDs, or
33 uses the 32-bit UID system calls properly otherwise.
40 (need to support whatever new 32-bit UID system calls are added to
45 At present, 32-bit UIDs _should_ work for:
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| /Documentation/devicetree/bindings/regulator/ |
| D | anatop-regulator.yaml | 25 anatop-vol-bit-shift:
27 description: u32 value representing the bit shift for the register.
29 anatop-vol-bit-width:
33 anatop-min-bit-val:
49 anatop-delay-bit-shift:
51 description: u32 value representing the bit shift for the step time register.
53 anatop-delay-bit-width:
57 anatop-enable-bit:
59 description: u32 value representing regulator enable bit offset.
68 - anatop-vol-bit-shift
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| /Documentation/devicetree/bindings/dma/stm32/ |
| D | st,stm32-mdma.yaml | 21 3. A 32bit mask specifying the DMA channel configuration
22 -bit 0-1: Source increment mode
26 -bit 2-3: Destination increment mode
30 -bit 8-9: Source increment offset size
31 0x0: byte (8bit)
32 0x1: half-word (16bit)
33 0x2: word (32bit)
34 0x3: double-word (64bit)
35 -bit 10-11: Destination increment offset size
36 0x0: byte (8bit)
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| /Documentation/networking/ |
| D | oa-tc6-framework.rst | 64 Each transmit data chunk begins with a 32-bit data header followed by a
70 chunk consists of a data chunk payload ending with a 32-bit data footer.
176 DNC (Bit 31) - Data-Not-Control flag. This flag specifies the type of SPI
177 transaction. For TX data chunks, this bit shall be ’1’.
181 SEQ (Bit 30) - Data Chunk Sequence. This bit is used to indicate an
184 NORX (Bit 29) - No Receive flag. The SPI host may set this bit to prevent
191 RSVD (Bit 28..24) - Reserved: All reserved bits shall be ‘0’.
193 VS (Bit 23..22) - Vendor Specific. These bits are implementation specific.
197 DV (Bit 21) - Data Valid flag. The SPI host uses this bit to indicate
201 the setting of the DV bit in the data header.
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| /Documentation/devicetree/bindings/hwmon/ |
| D | max6697.txt | 31 Alert bit mask. Alert disabled for bits set.
32 Select bit 0 for local temperature, bit 1..7 for remote temperatures.
35 Over-temperature bit mask. Over-temperature reporting disabled for
37 Select bit 0 for local temperature, bit 1..7 for remote temperatures.
44 specified as boolean, otherwise as per bit mask specified.
45 Only supported for remote temperatures (bit 1..7).
49 For MAX6581 only. Two values; first is bit mask, second is ideality
50 select value as per MAX6581 data sheet. Select bit 1..7 for remote
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| /Documentation/userspace-api/media/rc/ |
| D | rc-protos.rst | 17 Other things can be encoded too. Some IR protocols encode a toggle bit; this
20 toggle bit will invert from one IR message to the next.
41 * - rc-5 bit
43 - scancode bit
51 - Start bit, always set
57 - 2nd start bit in rc5, re-used as 6th command bit
63 - Toggle bit
78 where there the second stop bit is the 6th command bit, but inverted.
80 schemes. This bit is stored in bit 6 of the scancode, inverted. This is
85 This is much like rc-5 but one bit longer. The scancode is encoded
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| /Documentation/PCI/endpoint/ |
| D | pci-test-function.rst | 44 Bit 0 raise legacy IRQ
45 Bit 1 raise MSI IRQ
46 Bit 2 raise MSI-X IRQ
47 Bit 3 read command (read data from RC buffer)
48 Bit 4 write command (write data to RC buffer)
49 Bit 5 copy command (copy data from one RC buffer to another RC buffer)
59 Bit 0 read success
60 Bit 1 read fail
61 Bit 2 write success
62 Bit 3 write fail
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| /Documentation/arch/riscv/ |
| D | vector.rst | 21 please read :c:macro:`COMPAT_HWCAP_ISA_V` bit of :c:macro:`ELF_HWCAP` in the
27 argument consists of two 2-bit enablement statuses and a bit for inheritance
30 Enablement status is a tri-state value each occupying 2-bit of space in
43 arg: The control argument is a 5-bit value consisting of 3 parts, and
48 represents bit[1:0], bit[3:2], and bit[4]. bit[1:0] accounts for the
49 enablement status of current thread, and the setting at bit[3:2] takes place
50 at next execve(). bit[4] defines the inheritance mode of the setting in
51 bit[3:2].
53 * :c:macro:`PR_RISCV_V_VSTATE_CTRL_CUR_MASK`: bit[1:0]: Account for the
61 * :c:macro:`PR_RISCV_V_VSTATE_CTRL_NEXT_MASK`: bit[3:2]: Account for the
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| /Documentation/devicetree/bindings/edac/ |
| D | socfpga-eccmgr.txt | 3 The ECC Manager counts and corrects single bit errors and counts/handles
4 double bit errors which are uncorrectable.
19 - interrupts : Should be single bit error interrupt, then double bit error
27 - interrupts : Should be single bit error interrupt, then double bit error
63 - interrupts : Should be single bit error interrupt, then double bit error
75 - interrupts : Should be single bit error interrupt, then double bit error
82 - interrupts : Should be single bit error interrupt, then double bit error
90 - interrupts : Should be single bit error interrupt, then double bit error
98 - interrupts : Should be single bit error interrupt, then double bit error
106 - interrupts : Should be single bit error interrupt, then double bit error
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| /Documentation/devicetree/bindings/mmc/ |
| D | sdhci.txt | 7 - sdhci-caps-mask: The sdhci capabilities register is incorrect. This 64bit
8 property corresponds to the bits in the sdhci capability register. If the bit
9 is on in the mask then the bit is incorrect in the register and should be
11 - sdhci-caps: The sdhci capabilities register is incorrect. This 64bit
13 bit is on in the property then the bit should be turned on.
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| /Documentation/devicetree/bindings/soc/imx/ |
| D | fsl,imx-anatop.yaml | 76 anatop-vol-bit-shift = <8>;
77 anatop-vol-bit-width = <5>;
78 anatop-min-bit-val = <0>;
81 anatop-enable-bit = <0>;
91 anatop-vol-bit-shift = <0>;
92 anatop-vol-bit-width = <5>;
94 anatop-delay-bit-shift = <24>;
95 anatop-delay-bit-width = <2>;
96 anatop-min-bit-val = <1>;
108 anatop-vol-bit-shift = <18>;
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| /Documentation/devicetree/bindings/leds/ |
| D | register-bit-led.yaml | 4 $id: http://devicetree.org/schemas/leds/register-bit-led.yaml#
7 title: Register Bit LEDs
13 Register bit leds are used with syscon multifunctional devices where single
14 bits in a certain register can turn on/off a single LED. The register bit LEDs
25 The unit-address is in the form of @<reg addr>,<bit offset>
29 const: register-bit-led
38 bit mask for the bit controlling this LED in the register
70 compatible = "register-bit-led";
79 compatible = "register-bit-led";
87 compatible = "register-bit-led";
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| /Documentation/input/devices/ |
| D | elantech.rst | 118 calculating a parity bit for the last 3 bytes of each packet. The driver
183 bit 7 6 5 4 3 2 1 0
197 bit 7 6 5 4 3 2 1 0
240 bit 7 6 5 4 3 2 1 0
244 some models have M as byte 3 odd parity bit
246 p1..p2 = byte 1 and 2 odd parity bit
251 bit 7 6 5 4 3 2 1 0
259 bit 7 6 5 4 3 2 1 0
268 bit 7 6 5 4 3 2 1 0
289 bit 7 6 5 4 3 2 1 0
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| /Documentation/devicetree/bindings/clock/ti/ |
| D | gate.txt | 38 - ti,bit-shift : bit shift for programming the clock gate, invalid for
40 - ti,set-bit-to-disable : inverts default gate programming. Setting the bit
41 gates the clock and clearing the bit ungates the clock.
49 ti,bit-shift = <25>;
57 ti,bit-shift = <23>;
65 ti,bit-shift = <0>;
73 ti,bit-shift = <1>;
86 ti,bit-shift = <0x1b>;
88 ti,set-bit-to-disable;
95 ti,bit-shift = <3>;
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