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/Documentation/ABI/stable/
Dsysfs-driver-misc-cp5005 Description: Version of the FPGA configuration bitstream as printable string.
14 bitstream on reset. Normal FPGA behavior and default is to keep
15 configuration bitstream and to only reset the configured logic.
18 configuration bitstream with a simple reboot. Otherwise it is
20 configuration bitstream.
23 1 = keep configuration bitstream on reset, default
24 0 = reload configuration bitstream on reset
/Documentation/ABI/testing/
Dsysfs-driver-genwqe4 Description: Unique bitstream identification e.g.
21 Description: Currently active bitstream. 1 is default, 0 is backup.
26 Description: Interface to set the next bitstream to be used.
31 Description: Interface to trigger a PCIe card reset to reload the bitstream.
38 If successfully, the card will come back with the bitstream set
Ddebugfs-driver-genwqe58 Description: Comprehensive summary of bitstream version and software
59 version. Used bitstream and bitstream clocking information.
Dsysfs-class-fpga-manager44 error or incompatible bitstream image. The intent of this
Dsysfs-devices-platform-stratix10-rsu34 0xF001 bitstream error
36 0xF003 bitstream corruption
/Documentation/admin-guide/media/
Dvisl.rst43 - keep_bitstream_buffers: Controls whether bitstream (i.e. OUTPUT) buffers are
141 **/sys/kernel/debug/visl/bitstream** with OUTPUT buffer data according to the
150 snprintf(name, 32, "bitstream%d", run->src->sequence);
158 $ xxd /sys/kernel/debug/visl/bitstream/bitstream0
172 $ xxd /sys/kernel/debug/visl/bitstream/bitstream1
/Documentation/devicetree/bindings/pwm/
Dmicrochip,corepwm.yaml43 mode is possible for each channel, and is set by the bitstream programmed to the
60 core, set at instantiation and by the bitstream programmed to the FPGA, determines
/Documentation/staging/
Dlzo.rst88 common case for zram. This modifies the bitstream in a backwards compatible way
105 17 : bitstream version. If the first byte is 17, and compressed
107 versioned bitstream), the next byte gives the bitstream version
109 Otherwise, the bitstream version is 0.
/Documentation/devicetree/bindings/fpga/
Dlattice-machxo2-spi.txt3 Lattice MachXO2 FPGAs support a method of loading the bitstream over
Daltera-passive-serial.txt3 Altera FPGAs support a method of loading the bitstream over what is
Dmicrochip,mpf-spi-fpga-mgr.yaml14 load the bitstream in .dat format.
Dlattice,sysconfig.yaml17 Programming of ECP5 is done by writing uncompressed bitstream image in .bit
Dxlnx,fpga-selectmap.yaml13 Xilinx 7 Series FPGAs support a method of loading the bitstream over a
Dxlnx,fpga-slave-serial.yaml13 Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the bitstream
/Documentation/devicetree/bindings/media/
Damlogic,gx-vdec.yaml16 except for the hardware bitstream parser that makes use of an undocumented
20 - ESPARSER is a bitstream parser that outputs to a VIFIFO. Further VDEC blocks
Dnxp,imx8-jpeg.yaml36 - description: AXI DMA engine clock for fetching JPEG bitstream from memory (per)
Dnvidia,tegra-vde.yaml98 <0x6001b000 0x1000>, /* Video Bitstream Engine */
/Documentation/devicetree/bindings/
Dxilinx.txt15 to be recompiled every time the FPGA bitstream is resynthesized.
18 generate a new device tree each time the FPGA bitstream changes. The
108 bitstream stored on a CF card. It can also be used as a generic CF
/Documentation/userspace-api/media/v4l/
Dext-ctrls-codec-stateless.rst27 bitstream) for the associated H264 slice data. This includes the
29 pipeline for H264. The bitstream parameters are defined according
172 bitstream) for the associated H264 slice data. This includes the
174 pipeline for H264. The bitstream parameters are defined according
277 Specifies the scaling matrix (as extracted from the bitstream) for
278 the associated H264 slice data. The bitstream parameters are
311 Specifies the slice parameters (as extracted from the bitstream)
314 for H264. The bitstream parameters are defined according to
522 Specifies the decode parameters (as extracted from the bitstream)
525 for H264. The bitstream parameters are defined according to
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Dpixfmt-compressed.rst64 without the start code, as extracted from the H264 bitstream.
118 - MPEG-2 parsed slice data, as extracted from the MPEG-2 bitstream.
209 - HEVC parsed slice data, as extracted from the HEVC bitstream.
/Documentation/devicetree/bindings/soc/microchip/
Dmicrochip,mpfs-sys-controller.yaml29 microchip,bitstream-flash:
/Documentation/devicetree/bindings/net/can/
Dctu,ctucanfd.yaml21 …[4] PDF : https://dspace.cvut.cz/bitstream/handle/10467/80366/F3-DP-2019-Jerabek-Martin-Jerabek-th…
/Documentation/devicetree/bindings/sound/
Dfsl,micfil.yaml14 from a PDM microphone bitstream in a configurable output sampling rate.
/Documentation/devicetree/bindings/ata/
Dsata_highbank.yaml42 description: Maps port numbers to offsets within the SGPIO bitstream.
/Documentation/devicetree/bindings/mips/img/
Dxilfpga.txt76 When the example project bitstream is loaded, the cpu_reset button

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