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/Documentation/devicetree/bindings/fpga/
Dfpga-bridge.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/fpga-bridge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: FPGA Bridge
10 - Michal Simek <michal.simek@amd.com>
14 pattern: "^fpga-bridge(@.*|-([0-9]|[1-9][0-9]+))?$"
16 bridge-enable:
18 0 if driver should disable bridge at startup
19 1 if driver should enable bridge at startup
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Daltr,freeze-bridge-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/altr,freeze-bridge-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Altera Freeze Bridge Controller
10 The Altera Freeze Bridge Controller manages one or more freeze bridges.
12 changes from passing through the bridge. The controller can also
13 unfreeze/enable the bridges which allows traffic to pass through the bridge
17 - Xu Yilun <yilun.xu@intel.com>
20 - $ref: fpga-bridge.yaml#
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Daltr,socfpga-fpga2sdram-bridge.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/altr,socfpga-fpga2sdram-bridge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Altera FPGA To SDRAM Bridge
10 - Xu Yilun <yilun.xu@intel.com>
13 - $ref: fpga-bridge.yaml#
17 const: altr,socfpga-fpga2sdram-bridge
23 - compatible
28 - |
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Daltr,socfpga-hps2fpga-bridge.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/altr,socfpga-hps2fpga-bridge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Altera FPGA/HPS Bridge
10 - Xu Yilun <yilun.xu@intel.com>
13 - $ref: fpga-bridge.yaml#
18 - altr,socfpga-lwhps2fpga-bridge
19 - altr,socfpga-hps2fpga-bridge
20 - altr,socfpga-fpga2hps-bridge
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Dxlnx,pr-decoupler.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,pr-decoupler.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
13 - $ref: fpga-bridge.yaml#
18 which prevents signal changes from passing through the bridge. The controller
19 can also couple / enable the bridges which allows traffic to pass through the
20 bridge normally.
22 is compatible with the Xilinx LogiCORE pr-decoupler. The Dynamic Function
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/Documentation/devicetree/bindings/ata/
Dcortina,gemini-sata-bridge.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/cortina,gemini-sata-bridge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cortina Systems Gemini SATA Bridge
10 - Linus Walleij <linus.walleij@linaro.org>
13 The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that
19 const: cortina,gemini-sata-bridge
28 reset-names:
30 - const: sata0
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/Documentation/devicetree/bindings/display/bridge/
Dsimple-bridge.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/simple-bridge.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Transparent non-programmable DRM bridges
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
11 - Maxime Ripard <mripard@kernel.org>
14 This binding supports transparent non-programmable bridges that don't require
20 - items:
21 - enum:
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Dchipone,icn6211.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/chipone,icn6211.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Chipone ICN6211 MIPI-DSI to RGB Converter bridge
10 - Jagan Teki <jagan@amarulasolutions.com>
13 ICN6211 is MIPI-DSI to RGB Converter bridge from chipone.
21 - chipone,icn6211
27 clock-names:
36 enable-gpios:
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Dti,dlpc3433.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/ti,dlpc3433.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI DLPC3433 MIPI DSI to DMD bridge
10 - Jagan Teki <jagan@amarulasolutions.com>
11 - Christopher Vollo <chris@renewoutreach.org>
14 TI DLPC3433 is a MIPI DSI based display controller bridge
30 - 0x1b
31 - 0x1d
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Dti,sn65dsi86.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/ti,sn65dsi86.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SN65DSI86 DSI to eDP bridge chip
10 - Douglas Anderson <dianders@chromium.org>
13 The Texas Instruments SN65DSI86 bridge takes MIPI DSI in and outputs eDP.
23 enable-gpios:
27 suspend-gpios:
29 description: GPIO specifier for GPIO1 pin on bridge (active low).
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Dti,sn65dsi83.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/ti,sn65dsi83.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SN65DSI83 and SN65DSI84 DSI to LVDS bridge chip
10 - Marek Vasut <marex@denx.de>
13 Texas Instruments SN65DSI83 1x Single-link MIPI DSI
14 to 1x Single-link LVDS
16 Texas Instruments SN65DSI84 1x Single-link MIPI DSI
17 to 1x Dual-link or 2x Single-link LVDS
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/Documentation/devicetree/bindings/perf/
Dapm-xgene-pmu.txt1 * APM X-Gene SoC PMU bindings
3 This is APM X-Gene SoC PMU (Performance Monitoring Unit) module.
6 L3C - L3 cache controller
7 IOB - IO bridge
8 MCB - Memory controller bridge
9 MC - Memory controller
14 - compatible : Shall be "apm,xgene-pmu" for revision 1 or
15 "apm,xgene-pmu-v2" for revision 2.
16 - regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
17 - regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
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/Documentation/i2c/busses/
Di2c-ali15x3.rst2 Kernel driver i2c-ali15x3
6 * Acer Labs, Inc. ALI 1533 and 1543C (south bridge)
12 - Frodo Looijaard <frodol@dds.nl>,
13 - Philip Edelbrock <phil@netroedge.com>,
14 - Mark D. Studebaker <mdsxyz123@yahoo.com>
17 -----------------
24 -----
33 modprobe i2c-ali15x3 force_addr=0xe800
40 -----------
45 The M1543C is a South bridge for desktop systems.
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Di2c-sis630.rst2 Kernel driver i2c-sis630
7 630 chipset (Datasheet: available at http://www.sfr-fresh.com/linux)
13 - Alexander Malysh <amalysh@web.de>
14 - Amaury Decrême <amaury.decreme@gmail.com> - SiS964 support
17 -----------------
20 force = [1|0] Forcibly enable the SIS630. DANGEROUS!
33 -----------
40 00:00.0 Host bridge: Silicon Integrated Systems [SiS] 630 Host (rev 31)
41 00:01.0 ISA bridge: Silicon Integrated Systems [SiS] 85C503/5513
45 00:00.0 Host bridge: Silicon Integrated Systems [SiS] 730 Host (rev 02)
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Di2c-ali1535.rst2 Kernel driver i2c-ali1535
6 * Acer Labs, Inc. ALI 1535 (south bridge)
12 - Frodo Looijaard <frodol@dds.nl>,
13 - Philip Edelbrock <phil@netroedge.com>,
14 - Mark D. Studebaker <mdsxyz123@yahoo.com>,
15 - Dan Eaton <dan.eaton@rocketlogix.com>,
16 - Stephen Rousset<stephen.rousset@rocketlogix.com>
19 -----------
22 M1535 South Bridge.
24 The M1535 is a South bridge for portable systems. It is very similar to the
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Di2c-piix4.rst2 Kernel driver i2c-piix4
9 * ServerWorks OSB4, CSB5, CSB6, HT-1000 and HT-1100 southbridges
18 * AMD Hudson-2, ML, CZ
26 - Frodo Looijaard <frodol@dds.nl>
27 - Philip Edelbrock <phil@netroedge.com>
31 -----------------
34 Forcibly enable the PIIX4. DANGEROUS!
36 Forcibly enable the PIIX4 at the given address. EXTREMELY DANGEROUS!
40 -----------
45 SMBus - you can not access it on I2C levels. The good news is that it
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/Documentation/networking/device_drivers/ethernet/ti/
Dam65_nuss_cpsw_switchdev.rst1 .. SPDX-License-Identifier: GPL-2.0
14 ip -d link show dev sw0p1 | grep switchid
23 - The driver is operating in multi-mac mode by default, thus
29 See Documentation/networking/devlink/am65-nuss-cpsw-switch.rst
40 This can be done regardless of the state of Port's netdev devices - UP/DOWN, but
41 Port's netdev devices have to be in UP before joining to the bridge to avoid
42 overwriting of bridge configuration as CPSW switch driver completely reloads its
45 When the both interfaces joined the bridge - CPSW switch driver will enable
50 Bridge setup
58 ip link add name br0 type bridge
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Dcpsw_switchdev.rst1 .. SPDX-License-Identifier: GPL-2.0
17 ip -d link show dev sw0p1 | grep switchid
26 - The new (cpsw_new.c) driver is operating in dual-emac mode by default, thus
30 - optimized promiscuous mode: The P0_UNI_FLOOD (both ports) is enabled in
34 to the same bridge, but without enabling "switch" mode, or to different
36 - learning disabled on ports as it make not too much sense for
37 segregated ports - no forwarding in HW.
38 - enabled basic support for devlink.
47 name switch_mode type driver-specific
50 name ale_bypass type driver-specific
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/Documentation/ABI/testing/
Dsysfs-bus-iio-adc-ad71923 Contact: linux-iio@vger.kernel.org
5 This attribute, if available, is used to enable the AC
12 Contact: linux-iio@vger.kernel.org
15 bridge power down switch found on some converters.
16 In bridge applications, such as strain gauges and load cells,
17 the bridge itself consumes the majority of the current in the
19 the bridge can be disconnected (when it is not being used
24 Contact: linux-iio@vger.kernel.org
29 What: /sys/bus/iio/devices/iio:deviceX/in_voltage2-voltage2_shorted_raw
31 Contact: linux-iio@vger.kernel.org
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/Documentation/devicetree/bindings/pci/
Dpci.txt3 PCI Bus Binding to: IEEE Std 1275-1994
4 https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf
9 https://www.devicetree.org/open-firmware/practice/imap/imap0_9d.pdf
11 Additionally to the properties specified in the above standards a host bridge
14 - linux,pci-domain:
15 If present this property assigns a fixed PCI domain number to a host bridge,
20 number for each host bridge in the system must be unique.
21 - max-link-speed:
27 - reset-gpios:
30 - supports-clkreq:
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/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/
Dswitchdev.rst1 .. SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
12 Bridge offload
15 The mlx5 driver implements support for offloading bridge rules when in switchdev
16 mode. Linux bridge FDBs are automatically offloaded when mlx5 switchdev
17 representor is attached to bridge.
19 - Change device to switchdev mode::
23 - Attach mlx5 switchdev representor 'enp8s0f0' to bridge netdev 'bridge1'::
28 -----
30 Following bridge VLAN functions are supported by mlx5:
32 - VLAN filtering (including multiple VLANs per port)::
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/Documentation/devicetree/bindings/display/panel/
Dolimex,lcd-olinuxino.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/display/panel/olimex,lcd-olinuxino.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Olimex Ltd. LCD-OLinuXino bridge panel.
10 - Stefan Mavrodiev <stefan@olimex.com>
13 This device can be used as bridge between a host controller and LCD panels.
15 - LCD-OLinuXino-4.3TS
16 - LCD-OLinuXino-5
17 - LCD-OLinuXino-7
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/Documentation/networking/dsa/
Db53.rst1 .. SPDX-License-Identifier: GPL-2.0
20 The switch is, if possible, configured to enable a Broadcom specific 4-bytes
30 configuration described in the :ref:`dsa-config-showcases`.
33 ----------------------------------
38 See :ref:`dsa-tagged-configuration`.
41 -------------------------------------
48 The configuration slightly differ from the :ref:`dsa-vlan-configuration`.
54 In difference to the configuration described in :ref:`dsa-vlan-configuration`
57 VLAN configuration in the bridge showcase.
61 The configuration can only be set up via VLAN tagging and bridge setup.
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/Documentation/PCI/
Dmsi-howto.rst1 .. SPDX-License-Identifier: GPL-2.0
17 to change your driver to use MSI or MSI-X and some basic diagnostics to
28 in PCI 3.0 to allow each interrupt to be masked individually. The MSI-X
32 Devices may support both MSI and MSI-X, but only one can be enabled at
40 traditional pin-based interrupts.
42 Pin-based PCI interrupts are often shared amongst several devices.
47 When a device writes data to memory, then raises a pin-based interrupt,
49 arrived in memory (this becomes more likely with devices behind PCI-PCI
54 Using MSIs avoids this problem as the interrupt-generating write cannot
58 PCI devices can only support a single pin-based interrupt per function.
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/Documentation/networking/
Dnet_failover.rst1 .. SPDX-License-Identifier: GPL-2.0
23 This can be used by paravirtual drivers to enable an alternate low latency
28 virtio-net accelerated datapath: STANDBY mode
31 net_failover enables hypervisor controlled accelerated datapath to virtio-net
34 To support this, the hypervisor needs to enable VIRTIO_NET_F_STANDBY
35 feature on the virtio-net interface and assign the same MAC address to both
36 virtio-net and VF interfaces.
49 <alias name='ua-backup0'/>
56 <teaming type='transient' persistent='ua-backup0'/>
59 In this configuration, the first device definition is for the virtio-net
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