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/Documentation/devicetree/bindings/i2c/
Dopencores,i2c-ocores.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/opencores,i2c-ocores.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Korsgaard <peter@korsgaard.com>
11 - Andrew Lunn <andrew@lunn.ch>
14 - $ref: /schemas/i2c/i2c-controller.yaml#
19 - items:
20 - enum:
21 - sifive,fu740-c000-i2c # Opencore based IP block FU740-C000 SoC
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Di2c-pca-platform.txt4 parallel-bus microcontrollers/microprocessors and the serial I2C-bus
5 and allows the parallel bus system to communicate bi-directionally
6 with the I2C-bus.
10 - reg : Offset and length of the register set for the device
11 - compatible : one of "nxp,pca9564" or "nxp,pca9665"
14 - interrupts : the interrupt number
15 - reset-gpios : gpio specifier for gpio connected to RESET_N pin. As the line
17 - clock-frequency : I2C bus frequency.
22 #address-cells = <1>;
23 #size-cells = <0>;
[all …]
Daspeed,i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rayn Chen <rayn_chen@aspeedtech.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - aspeed,ast2400-i2c-bus
19 - aspeed,ast2500-i2c-bus
20 - aspeed,ast2600-i2c-bus
25 - description: address offset and range of bus
26 - description: address offset and range of bus buffer
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Di2c-opal.txt1 Device-tree bindings for I2C OPAL driver
2 ----------------------------------------
6 perspective, the properties of use are "ibm,port-name" and "ibm,opal-id".
10 - reg: Port-id within a given master
11 - compatible: must be "ibm,opal-i2c"
12 - ibm,opal-id: Refers to a specific bus and used to identify it when calling
14 - bus-frequency: Operating frequency of the i2c bus (in HZ). Informational for
18 - ibm,port-name: Firmware provides this name that uniquely identifies the i2c
23 a P8 on-chip bus.
27 i2c-bus@0 {
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Di2c-img-scb.txt1 IMG Serial Control Bus (SCB) I2C Controller
4 - compatible: "img,scb-i2c"
5 - reg: Physical base address and length of controller registers
6 - interrupts: Interrupt number used by the controller
7 - clocks : Should contain a clock specifier for each entry in clock-names
8 - clock-names : Should contain the following entries:
11 - clock-frequency: The I2C bus frequency in Hz
12 - #address-cells: Should be <1>
13 - #size-cells: Should be <0>
18 compatible = "img,scb-i2c";
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Dnuvoton,npcm7xx-i2c.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/i2c/nuvoton,npcm7xx-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 I2C bus controllers of the NPCM series support both master and
15 - Tali Perry <tali.perry1@gmail.com>
20 - nuvoton,npcm750-i2c
21 - nuvoton,npcm845-i2c
31 description: Reference clock for the I2C bus
33 clock-frequency:
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Dapple,i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sven Peter <sven@svenpeter.dev>
15 The bus is used to communicate with e.g. USB PD chips or the speaker
19 - $ref: /schemas/i2c/i2c-controller.yaml#
24 - enum:
25 - apple,t8103-i2c
26 - apple,t8112-i2c
27 - apple,t6000-i2c
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Di2c-altera.txt6 - compatible : should be "altr,softip-i2c-v1.0"
7 - reg : Offset and length of the register set for the device
8 - interrupts : <IRQ> where IRQ is the interrupt number.
9 - clocks : phandle to input clock.
10 - #address-cells = <1>;
11 - #size-cells = <0>;
14 - clock-frequency : desired I2C bus clock frequency in Hz.
17 - fifo-size : Size of the RX and TX FIFOs in bytes.
18 - Child nodes conforming to i2c bus binding
23 compatible = "altr,softip-i2c-v1.0";
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Di2c-hix5hd2.txt4 - compatible: Must be "hisilicon,hix5hd2-i2c"
5 - reg: physical base address of the controller and length of memory mapped
7 - interrupts: interrupt number to the cpu.
8 - #address-cells = <1>;
9 - #size-cells = <0>;
10 - clocks: phandles to input clocks.
13 - clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000
14 - Child nodes conforming to i2c bus binding
18 compatible = "hisilicon,hix5hd2-i2c";
22 #address-cells = <1>;
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/Documentation/ABI/testing/
Dsysfs-bus-iio-impedance-analyzer-ad59331 What: /sys/bus/iio/devices/iio:deviceX/out_altvoltageY_frequency_start
4 Contact: linux-iio@vger.kernel.org
6 Frequency sweep start frequency in Hz.
8 What: /sys/bus/iio/devices/iio:deviceX/out_altvoltageY_frequency_increment
11 Contact: linux-iio@vger.kernel.org
13 Frequency increment in Hz (step size) between consecutive
14 frequency points along the sweep.
16 What: /sys/bus/iio/devices/iio:deviceX/out_altvoltageY_frequency_points
19 Contact: linux-iio@vger.kernel.org
21 Number of frequency points (steps) in the frequency sweep.
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Dsysfs-platform-dptf1 What: /sys/bus/platform/devices/INT3407:00/dptf_power/charger_type
4 Contact: linux-acpi@vger.kernel.org
6 (RO) The charger type - Traditional, Hybrid or NVDC.
8 What: /sys/bus/platform/devices/INT3407:00/dptf_power/adapter_rating_mw
11 Contact: linux-acpi@vger.kernel.org
16 What: /sys/bus/platform/devices/INT3407:00/dptf_power/max_platform_power_mw
19 Contact: linux-acpi@vger.kernel.org
24 What: /sys/bus/platform/devices/INT3407:00/dptf_power/platform_power_source
27 Contact: linux-acpi@vger.kernel.org
33 - 0x00 = DC
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Dsysfs-bus-iio-dac-ltc26881 What: /sys/bus/iio/devices/iio:deviceX/out_voltageY_dither_en
3 Contact: linux-iio@vger.kernel.org
8 - disable dither operation;
9 - change dither parameters (eg: frequency, phase...);
10 - enabled dither operation
12 What: /sys/bus/iio/devices/iio:deviceX/out_voltageY_dither_raw
14 Contact: linux-iio@vger.kernel.org
20 What: /sys/bus/iio/devices/iio:deviceX/out_voltageY_dither_raw_available
22 Contact: linux-iio@vger.kernel.org
26 What: /sys/bus/iio/devices/iio:deviceX/out_voltageY_dither_offset
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Dsysfs-bus-iio-frequency-adf43501 What: /sys/bus/iio/devices/iio:deviceX/out_altvoltageY_frequency_resolution
3 Contact: linux-iio@vger.kernel.org
5 Stores channel Y frequency resolution/channel spacing in Hz.
7 the fractional-N PLL. It is assumed that the algorithm
11 What: /sys/bus/iio/devices/iio:deviceX/out_altvoltageY_refin_frequency
13 Contact: linux-iio@vger.kernel.org
15 Sets channel Y REFin frequency in Hz. In some clock chained
16 applications, the reference frequency used by the PLL may
18 adjust the reference frequency accordingly.
Dsysfs-driver-intel-xe-hwmon1 What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/power1_max
4 Contact: intel-xe@lists.freedesktop.org
7 The power controller will throttle the operating frequency
15 What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/power1_rated_max
18 Contact: intel-xe@lists.freedesktop.org
24 What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/energy1_input
27 Contact: intel-xe@lists.freedesktop.org
32 What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/power1_max_interval
35 Contact: intel-xe@lists.freedesktop.org
41 What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/power2_max
[all …]
Dsysfs-bus-iio-adc-ad41301 What: /sys/bus/iio/devices/iio:deviceX/in_voltage-voltage_filter_mode_available
3 Contact: linux-iio@vger.kernel.org
7 * "sinc4" - Sinc 4. Excellent noise performance. Long
10 * "sinc4+sinc1" - Sinc4 + averaging by 8. Low 1st conversion
13 * "sinc3" - Sinc3. Moderate 1st conversion time.
16 * "sinc3+rej60" - Sinc3 + 60Hz rejection. At a sampling
17 frequency of 50Hz, achieves simultaneous 50Hz and 60Hz
20 * "sinc3+sinc1" - Sinc3 + averaging by 8. Low 1st conversion
21 time. Best used with a sampling frequency of at least
24 * "sinc3+pf1" - Sinc3 + Post Filter 1. 53dB rejection @
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Dsysfs-driver-intel-i915-hwmon1 What: /sys/bus/pci/drivers/i915/.../hwmon/hwmon<i>/in0_input
4 Contact: intel-gfx@lists.freedesktop.org
9 What: /sys/bus/pci/drivers/i915/.../hwmon/hwmon<i>/power1_max
12 Contact: intel-gfx@lists.freedesktop.org
15 The power controller will throttle the operating frequency
23 What: /sys/bus/pci/drivers/i915/.../hwmon/hwmon<i>/power1_rated_max
26 Contact: intel-gfx@lists.freedesktop.org
31 What: /sys/bus/pci/drivers/i915/.../hwmon/hwmon<i>/power1_max_interval
34 Contact: intel-gfx@lists.freedesktop.org
40 What: /sys/bus/pci/drivers/i915/.../hwmon/hwmon<i>/power1_crit
[all …]
/Documentation/devicetree/bindings/mmc/
Dcavium-mmc.txt10 - compatible : should be one of:
11 cavium,octeon-6130-mmc
12 cavium,octeon-7890-mmc
13 cavium,thunder-8190-mmc
14 cavium,thunder-8390-mmc
15 mmc-slot
16 - reg : mmc controller base registers
17 - clocks : phandle
20 - for cd, bus-width and additional generic mmc parameters
22 - cavium,cmd-clk-skew : number of coprocessor clocks before sampling command
[all …]
Ddavinci_mmc.txt9 - compatible:
10 Should be "ti,da830-mmc": for da830, da850, dm365
11 Should be "ti,dm355-mmc": for dm355, dm644x
14 - bus-width: Number of data lines, can be <1>, <4>, or <8>, default <1>
15 - max-frequency: Maximum operating clock frequency, default 25MHz.
16 - dmas: List of DMA specifiers with the controller specific format
19 - dma-names: RX and TX DMA request names. These strings correspond
24 compatible = "ti,da830-mmc",
27 bus-width = <4>;
28 max-frequency = <50000000>;
[all …]
/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
Dfsl,qe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
18 Basically, it is a bus of devices, that could act more or less
27 - const: fsl,qe
28 - const: simple-bus
40 bus-frequency:
42 description: the clock frequency for QUICC Engine.
44 fsl,qe-num-riscs:
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/Documentation/devicetree/bindings/soc/fsl/cpm_qe/cpm/
Di2c.txt3 The I2C controller is expressed as a bus under the CPM node.
6 - compatible : "fsl,cpm1-i2c", "fsl,cpm2-i2c"
7 - reg : On CPM2 devices, the second resource doesn't specify the I2C
10 - #address-cells : Should be one. The cell is the i2c device address with
12 - #size-cells : Should be zero.
13 - clock-frequency : Can be used to set the i2c clock frequency. If
14 unspecified, a default frequency of 60kHz is being used.
16 i2c drivers to find the bus to probe:
17 - linux,i2c-index : Can be used to hard code an i2c bus number. By default,
18 the bus number is dynamically assigned by the i2c core.
[all …]
/Documentation/devicetree/bindings/memory-controllers/
Drockchip,rk3399-dmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/rockchip,rk3399-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <briannorris@chromium.org>
15 - rockchip,rk3399-dmc
17 devfreq-events:
26 clock-names:
28 - const: dmc_clk
30 operating-points-v2: true
[all …]
/Documentation/devicetree/bindings/gpio/
Daspeed,sgpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Jeffery <andrew@aj.id.au>
17 - Support interrupt option for each input port and various interrupt
18 sensitivity option (level-high, level-low, edge-high, edge-low)
19 - Support reset tolerance option for each output port
20 - Directly connected to APB bus and its shift clock is from APB bus clock
22 - Co-work with external signal-chained TTL components (74LV165/74LV595)
27 - aspeed,ast2400-sgpio
[all …]
/Documentation/devicetree/bindings/media/
Dsamsung,s5c73m3.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11 - Sylwester Nawrocki <s.nawrocki@samsung.com>
14 The S5C73M3 camera ISP supports MIPI CSI-2 and parallel (ITU-R BT.656)
15 video data busses. The I2C bus is the main control bus and additionally the
16 SPI bus is used, mostly for transferring the firmware to and from the
17 device. Two slave device nodes corresponding to these control bus
18 interfaces are required and should be placed under respective bus
[all …]
/Documentation/devicetree/bindings/fsi/
Dfsi-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fsi/fsi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Eddie James <eajames@linux.ibm.com>
13 FSI (FRU (Field Replaceable Unit) Service Interface) is a two wire bus. The
14 FSI bus is connected to a CFAM (Common FRU Access Macro) which contains
18 "#address-cells":
21 "#size-cells":
24 '#interrupt-cells':
[all …]
/Documentation/devicetree/bindings/media/i2c/
Dmipi-ccs.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2014--2020 Intel Corporation
4 ---
5 $id: http://devicetree.org/schemas/media/i2c/mipi-ccs.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Sakari Ailus <sakari.ailus@linux.intel.com>
17 <URL:https://www.mipi.org/specifications/camera-command-set>.
24 Documentation/devicetree/bindings/media/video-interfaces.txt .
29 - items:
30 - const: mipi-ccs-1.1
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