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/Documentation/devicetree/bindings/bus/
Dsimple-pm-bus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/bus/simple-pm-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Simple Power-Managed Bus
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 A Simple Power-Managed Bus is a transparent bus that doesn't need a real
16 However, its bus controller is part of a PM domain, or under the control
17 of a functional clock. Hence, the bus controller's PM domain and/or
18 clock must be enabled for child devices connected to the bus (either
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Dqcom,ssc-block-bus.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/qcom,ssc-block-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: The AHB Bus Providing a Global View of the SSC Block on (some) qcom SoCs
10 - Michael Srba <Michael.Srba@seznam.cz>
13 This binding describes the dependencies (clocks, resets, power domains) which
14 need to be turned on in a sequence before communication over the AHB bus
27 - const: qcom,msm8998-ssc-block-bus
28 - const: qcom,ssc-block-bus
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Dfsl,imx8qxp-pixel-link-msi-bus.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX8qxp Pixel Link Medium Speed Interconnect (MSI) Bus
10 - Liu Ying <victor.liu@nxp.com>
13 i.MX8qxp pixel link MSI bus is used to control settings of PHYs, I/Os
14 sitting together with the PHYs. It is not the same as the MSI bus coming
15 from i.MX8 System Controller Unit (SCU) which is used to control power,
18 i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks,
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/Documentation/ABI/testing/
Dsysfs-driver-intel-xe-hwmon1 What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/power1_max
4 Contact: intel-xe@lists.freedesktop.org
5 Description: RW. Card reactive sustained (PL1) power limit in microwatts.
7 The power controller will throttle the operating frequency
8 if the power averaged over a window (typically seconds)
10 power limit is disabled, writing 0 disables the
11 limit. Writing values > 0 and <= TDP will enable the power limit.
15 What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/power1_rated_max
18 Contact: intel-xe@lists.freedesktop.org
19 Description: RO. Card default power limit (default TDP setting).
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Dsysfs-driver-intel-i915-hwmon1 What: /sys/bus/pci/drivers/i915/.../hwmon/hwmon<i>/in0_input
4 Contact: intel-gfx@lists.freedesktop.org
9 What: /sys/bus/pci/drivers/i915/.../hwmon/hwmon<i>/power1_max
12 Contact: intel-gfx@lists.freedesktop.org
13 Description: RW. Card reactive sustained (PL1/Tau) power limit in microwatts.
15 The power controller will throttle the operating frequency
16 if the power averaged over a window (typically seconds)
18 power limit is disabled, writing 0 disables the
19 limit. Writing values > 0 will enable the power limit.
23 What: /sys/bus/pci/drivers/i915/.../hwmon/hwmon<i>/power1_rated_max
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Dsysfs-platform-wilco-ec1 What: /sys/bus/platform/devices/GOOG000C\:00/boot_on_ac
6 when AC power is connected. This is useful for users who
11 What: /sys/bus/platform/devices/GOOG000C\:00/build_date
18 What: /sys/bus/platform/devices/GOOG000C\:00/build_revision
26 What: /sys/bus/platform/devices/GOOG000C\:00/model_number
34 What: /sys/bus/platform/devices/GOOG000C\:00/usb_charge
41 low power states:
43 - In S0, the port will always provide power.
44 - In S0ix, if usb_charge is enabled, then power will be
46 Else no power is supplied.
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Dsysfs-platform-dptf1 What: /sys/bus/platform/devices/INT3407:00/dptf_power/charger_type
4 Contact: linux-acpi@vger.kernel.org
6 (RO) The charger type - Traditional, Hybrid or NVDC.
8 What: /sys/bus/platform/devices/INT3407:00/dptf_power/adapter_rating_mw
11 Contact: linux-acpi@vger.kernel.org
13 (RO) Adapter rating in milliwatts (the maximum Adapter power).
16 What: /sys/bus/platform/devices/INT3407:00/dptf_power/max_platform_power_mw
19 Contact: linux-acpi@vger.kernel.org
21 (RO) Maximum platform power that can be supported by the battery
24 What: /sys/bus/platform/devices/INT3407:00/dptf_power/platform_power_source
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Dsysfs-bus-usb1 What: /sys/bus/usb/devices/<INTERFACE>/authorized
9 by writing INTERFACE to /sys/bus/usb/drivers_probe
10 This allows to avoid side-effects with drivers
15 What: /sys/bus/usb/devices/usbX/interface_authorized_default
22 What: /sys/bus/usb/device/.../authorized
28 drivers, non-authorized one are not. By default, wired
31 What: /sys/bus/usb/drivers/.../new_id
33 Contact: linux-usb@vger.kernel.org
48 # echo "8086 10f5" > /sys/bus/usb/drivers/foo/new_id
53 # echo "0458 7045 0 0458 704c" > /sys/bus/usb/drivers/foo/new_id
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Dsysfs-platform-dfl-fme1 What: /sys/bus/platform/devices/dfl-fme.0/ports_num
5 Description: Read-only. One DFL FPGA device may have more than 1
9 What: /sys/bus/platform/devices/dfl-fme.0/bitstream_id
13 Description: Read-only. It returns Bitstream (static FPGA region)
17 What: /sys/bus/platform/devices/dfl-fme.0/bitstream_metadata
21 Description: Read-only. It returns Bitstream (static FPGA region) meta
25 What: /sys/bus/platform/devices/dfl-fme.0/cache_size
29 Description: Read-only. It returns cache size of this FPGA device.
31 What: /sys/bus/platform/devices/dfl-fme.0/fabric_version
35 Description: Read-only. It returns fabric version of this FPGA device.
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Dsysfs-bus-iio-inv_icm426001 What: /sys/bus/iio/devices/iio:deviceX/in_accel_power_mode
3 Contact: linux-iio@vger.kernel.org
5 Accelerometer power mode. Setting this attribute will set the
6 requested power mode to use if the ODR support it. If ODR
7 support only 1 mode, power mode will be enforced.
9 power mode if the sensor is on, or the requested value if the
13 What: /sys/bus/iio/devices/iio:deviceX/in_accel_power_mode_available
15 Contact: linux-iio@vger.kernel.org
17 List of available accelerometer power modes that can be set in
Dsysfs-bus-iio-vf6101 What: /sys/bus/iio/devices/iio:deviceX/in_conversion_mode
3 Contact: linux-iio@vger.kernel.org
6 available modes are "normal", "high-speed" and "low-power",
10 What: /sys/bus/iio/devices/iio:deviceX/out_conversion_mode
12 Contact: linux-iio@vger.kernel.org
15 The two available modes are "high-power" and "low-power",
16 where "low-power" mode is the default mode.
Dsysfs-platform-dfl-port1 What: /sys/bus/platform/devices/dfl-port.0/id
5 Description: Read-only. It returns id of this port. One DFL FPGA device
9 What: /sys/bus/platform/devices/dfl-port.0/afu_id
13 Description: Read-only. User can program different PR bitstreams to FPGA
18 What: /sys/bus/platform/devices/dfl-port.0/power_state
22 Description: Read-only. It reports the APx (AFU Power) state, different APx
24 returns "0" - Normal / "1" - AP1 / "2" - AP2 / "6" - AP6.
26 What: /sys/bus/platform/devices/dfl-port.0/ap1_event
30 Description: Read-write. Read this file for AP1 (AFU Power State 1) event.
34 What: /sys/bus/platform/devices/dfl-port.0/ap2_event
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/Documentation/hwmon/
Dina209.rst6 * Burr-Brown / Texas Instruments INA209
10 Addresses scanned: -
16 - Paul Hays <Paul.Hays@cattail.ca>
17 - Ira W. Snyder <iws@ovro.caltech.edu>
18 - Guenter Roeck <linux@roeck-us.net>
22 -----------
24 The TI / Burr-Brown INA209 monitors voltage, current, and power on the high side
25 of a D.C. power supply. It can perform measurements and calculations in the
27 calibration multiplier to scale the displayed current and power values.
31 -------------
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Dina2xx.rst10 Addresses: I2C 0x40 - 0x4f
20 Addresses: I2C 0x40 - 0x4f
30 Addresses: I2C 0x40 - 0x4f
40 Addresses: I2C 0x40 - 0x4f
50 Addresses: I2C 0x40 - 0x4f
59 -----------
61 The INA219 is a high-side current shunt and power monitor with an I2C
65 The INA220 is a high or low side current shunt and power monitor with an I2C
68 The INA226 is a current shunt and power monitor with an I2C interface.
69 The INA226 monitors both a shunt voltage drop and bus supply voltage.
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Dtmp513.rst1 .. SPDX-License-Identifier: GPL-2.0
22 Eric Tremblay <etremblay@distech-controls.com>
25 -----------
28 The TMP512 (dual-channel) and TMP513 (triple-channel) are system monitors
29 that include remote sensors, a local temperature sensor, and a high-side current
31 temperatures, on-chip temperatures, and system voltage/power/current
35 -40 to + 125 degrees with a resolution of 0.0625 degree C.
44 **temp[1-4]_input**
46 **temp[1-4]_crit**
48 **temp[1-4]_crit_alarm**
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/Documentation/devicetree/bindings/soc/imx/
Dfsl,imx8mm-vpu-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MM VPU blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MM VPU blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the VPU peripherals
20 - const: fsl,imx8mm-vpu-blk-ctrl
21 - const: syscon
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/Documentation/devicetree/bindings/interconnect/
Dsamsung,exynos-bus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interconnect/samsung,exynos-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos SoC Bus and Interconnect
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
15 sub-blocks in SoC. Most Exynos SoCs share the common architecture for buses.
16 Generally, each bus of Exynos SoC includes a source clock and a power line,
17 which are able to change the clock frequency of the bus in runtime. To
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/Documentation/devicetree/bindings/media/
Dqcom,sdm845-venus.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/qcom,sdm845-venus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stanimir Varbanov <stanimir.varbanov@linaro.org>
17 - $ref: qcom,venus-common.yaml#
21 const: qcom,sdm845-venus
23 power-domains:
29 clock-names:
31 - const: core
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/Documentation/usb/
Dchipidea.rst6 -----------------------------------
12 -------------------------
29 otg-rev = <0x0200>;
30 adp-disable;
33 -------------------
35 1) Power up 2 Freescale i.MX6Q sabre SD boards with gadget class driver loaded
41 The A-device (with micro A plug inserted) should enumerate B-device.
45 On B-device::
47 echo 1 > /sys/bus/platform/devices/ci_hdrc.0/inputs/b_bus_req
49 B-device should take host role and enumerate A-device.
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/Documentation/driver-api/
Dslimbus.rst9 ----------------
10 SLIMbus (Serial Low Power Interchip Media Bus) is a specification developed by
11 MIPI (Mobile Industry Processor Interface) alliance. The bus uses master/slave
12 configuration, and is a 2-wire multi-drop implementation (clock, and data).
15 (System-on-Chip) and peripheral components (typically codec). SLIMbus uses
16 Time-Division-Multiplexing to accommodate multiple data channels, and
19 The control channel is used for various control functions such as bus
24 A data channel is used for data-transfer between 2 SLIMbus devices. Data
28 ---------------------
32 channel allocation. Every bus has 1 active manager.
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/Documentation/driver-api/driver-model/
Doverview.rst16 bus-specific drivers for bridges and devices by consolidating a set of data
19 Traditional driver models implemented some sort of tree-like structure
21 uniformity across the different bus types.
24 a bus and the devices that can appear under the bus. The unified bus
26 of common callbacks, such as device discovery during bus probing, bus
27 shutdown, bus power management, etc.
30 computer: namely the ability to do seamless device "plug and play", power
32 Microsoft (namely ACPI) ensures that almost every device on almost any bus
33 on an x86-compatible system can work within this paradigm. Of course,
34 not every bus is able to support all such operations, although most
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/Documentation/ABI/stable/
Dsysfs-bus-usb1 What: /sys/bus/usb/devices/.../power/persist
6 USB device directories can contain a file named power/persist.
8 not the "USB-Persist" facility is enabled for the device. For
12 For more information, see Documentation/driver-api/usb/persist.rst.
14 What: /sys/bus/usb/devices/.../power/autosuspend
20 power/autosuspend. This file holds the time (in seconds)
27 The autosuspend delay for newly-created devices is set to
30 What: /sys/bus/usb/device/.../power/connected_duration
37 connected to the machine. This file is read-only.
42 What: /sys/bus/usb/device/.../power/active_duration
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Dsysfs-bus-mhi1 What: /sys/bus/mhi/devices/.../serialnumber
7 one attempt to power up the device has been done. If read
8 without having the device power on at least once, the file will
12 What: /sys/bus/mhi/devices/.../oem_pk_hash
18 at least one attempt to power up the device has been done. If
19 read without having the device power on at least once, the file
23 What: /sys/bus/mhi/devices/.../soc_reset
28 a reset of last resort, and will require a complete re-init.
30 non-responsive, or as a means of loading new firmware as a
33 What: /sys/bus/mhi/devices/.../trigger_edl
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/Documentation/driver-api/pm/
Ddevices.rst1 .. SPDX-License-Identifier: GPL-2.0
7 Device Power Management Basics
10 :Copyright: |copy| 2010-2011 Rafael J. Wysocki <rjw@sisk.pl>, Novell Inc.
17 Most of the code in Linux is device drivers, so most of the Linux power
18 management (PM) code is also driver-specific. Most drivers will do very
22 This writeup gives an overview of how drivers interact with system-wide
23 power management goals, emphasizing the models and interfaces that are
25 background for the domain-specific work you'd do with any specific driver.
28 Two Models for Device Power Management
31 Drivers will use one or both of these models to put devices into low-power
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/Documentation/devicetree/bindings/leds/
Dleds-netxbig.txt1 Binding for the CPLD LEDs (GPIO extension bus) found on some LaCie/Seagate
5 - compatible: "lacie,netxbig-leds".
6 - gpio-ext: Phandle for the gpio-ext bus.
9 - timers: Timer array. Each timer entry is represented by three integers:
10 Mode (gpio-ext bus), delay_on and delay_off.
12 Each LED is represented as a sub-node of the netxbig-leds device.
14 Required sub-node properties:
15 - mode-addr: Mode register address on gpio-ext bus.
16 - mode-val: Mode to value mapping. Each entry is represented by two integers:
17 A mode and the corresponding value on the gpio-ext bus.
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