Searched full:caches (Results 1 – 25 of 105) sorted by relevance
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| /Documentation/block/ |
| D | writeback_cache_control.rst | 9 write back caches. That means the devices signal I/O completion to the
52 For devices that do not support volatile write caches there is no driver
57 For devices with volatile write caches the driver needs to tell the block layer
58 that it supports flushing caches by setting the
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| /Documentation/filesystems/nfs/ |
| D | rpc-cache.rst | 9 Caches subtitle
13 a wide variety of values to be caches.
15 There are a number of caches that are similar in structure though
17 of common code for managing these caches.
19 Examples of caches that are likely to be needed are:
105 includes it on a list of caches that will be regularly
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| D | pnfs.rst | 5 The are several inter-related caches. We have layouts which can
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| /Documentation/filesystems/ |
| D | 9p.rst | 136 cache=mode specifies a caching policy. By default, no caches are used.
142 0b00000000 all caches disabled, mmap disabled
143 0b00000001 file caches enabled
144 0b00000010 meta-data caches enabled
146 0b00001000 loose caches (no explicit consistency with server)
156 loose 0b00001111 (non-coherent file and meta-data caches)
164 IMPORTANT: loose caches (and by extension at the moment fscache)
240 /sys/fs/9p/caches. (applies only to cache=fscache)
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| /Documentation/core-api/ |
| D | cachetlb.rst | 125 us to properly handle systems whose caches are strict and require
133 indexed caches which must be flushed when virtual-->physical
135 indexed physically tagged caches of IA32 processors have no need to
136 implement these interfaces since the caches are fully synchronized
144 the caches. That is, after running, there will be no cache
153 the caches. That is, after running, there will be no cache
160 optimizations for VIPT caches.
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| /Documentation/arch/arm64/ |
| D | cpu-hotplug.rst | 29 e.g. New CPUs come with new caches, but the platform's cache topology is
30 described in a static table, the PPTT. How caches are shared between CPUs is
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| D | booting.rst | 174 - Caches, MMUs
183 coherent masters with caches enabled, this will typically require
185 System caches which respect the architected cache maintenance by VA
187 System caches which do not respect architected cache maintenance by VA
436 The requirements described above for CPU mode, caches, MMUs, architected
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| /Documentation/locking/ |
| D | percpu-rw-semaphore.rst | 10 is bouncing between L1 caches of the cores, causing performance
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| /Documentation/mm/ |
| D | slub.rst | 7 slab caches. SLUB always includes full debugging but it is off by default.
56 O Switch debugging off for caches that would have
82 a result of storing the metadata (for example, caches with PAGE_SIZE object
85 switch off debugging for such caches by default, use::
95 You can also enable options (e.g. sanity checks and poisoning) for all caches
391 For more information about current state of SLUB caches with the user tracking
393 /sys/kernel/debug/slab/<cache>/ (created only for caches with enabled user
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| D | page_tables.rst | 161 to physical address translations. It may use relatively small caches in hardware
162 called `Translation Lookaside Buffers (TLBs)` and `Page Walk Caches` to speed up
167 Walk Caches (on architectures that support them). If no translation is found,
225 storage or from other devices, and updates the MMU and its caches.
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| D | page_frags.rst | 25 The network stack uses two separate caches per CPU to handle fragment
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | pamu.txt | 61 second is the number of "ways". For direct-mapped caches,
67 second is the number of "ways". For direct-mapped caches,
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| /Documentation/hwmon/ |
| D | adc128d818.rst | 41 caches the alarm status for each sensor until it is at least reported
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| /Documentation/devicetree/bindings/iommu/ |
| D | qcom,tbu.yaml | 14 a Translation Lookaside Buffer (TLB) that caches page tables. TBUs provides
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| /Documentation/driver-api/md/ |
| D | raid5-cache.rst | 7 caches data to the RAID disks. The cache can be in write-through (supported
66 In write-back mode, MD also caches data in memory. The memory cache includes
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| /Documentation/ABI/stable/ |
| D | sysfs-fs-orangefs | 5 Counters and settings for various caches.
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| /Documentation/arch/powerpc/ |
| D | cpu_features.rst | 14 split instruction and data caches, and if the CPU supports the DOZE and NAP
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | ti,davinci-rproc.txt | 9 like L1 and/or L2 caches/SRAMs, an Interrupt Controller, an external memory
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| /Documentation/admin-guide/mm/ |
| D | numaperf.rst | 115 This numbering is different than CPU caches where the cache level (ex:
121 The memory-side caches are not directly addressable by software. When
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| /Documentation/staging/ |
| D | speculation.rst | 17 absence of data in caches. Such state may form side-channels which can be
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| /Documentation/virt/kvm/x86/ |
| D | errata.rst | 67 hardware, i.e. put the CPU caches into "no fill" mode when CR0.CD=1, even when
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| /Documentation/ABI/testing/ |
| D | sysfs-kernel-slab | 19 The aliases file is read-only and specifies how many caches
426 checks. Caches that enable sanity_checks cannot be merged with
427 caches that do not.
441 Shrinking slab caches might be expensive and can
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| /Documentation/admin-guide/device-mapper/ |
| D | writecache.rst | 5 The writecache target caches writes on persistent memory or on SSD. It
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| /Documentation/arch/arm/ |
| D | cluster-pm-race-avoidance.rst | 36 writing some hardware registers and invalidating large caches), other
203 caches).
376 down, for example by cleaning data caches and exiting
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| /Documentation/driver-api/ |
| D | edac.rst | 155 - CPU caches (L1 and L2)
167 caches. On such case, those can be represented via the following sysfs
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