Searched +full:can +full:- +full:disable (Results 1 – 25 of 608) sorted by relevance
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| /Documentation/hwmon/ |
| D | ibmpowernv.rst | 11 -----------
22 the DT maps to an attribute file in 'sysfs'. The node exports unique 'sensor-id'
26 -----------
28 CONFIG_SENSORS_IBMPOWERNV. It can also be built as module 'ibmpowernv'.
31 ----------------
36 fanX_fault - 0: No fail condition
37 - 1: Failing fan
43 tempX_enable Enable/disable all temperature sensors belonging to the
44 sub-group. In POWER9, this attribute corresponds to
45 each OCC. Using this attribute each OCC can be asked to
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| D | pwm-fan.rst | 1 Kernel driver pwm-fan
5 generic PWM interface thus it is hardware independent. It can be used on
12 -----------
15 a PWM output. It uses the generic PWM interface, thus it can be used with
27 0 -> disable pwm and regulator
28 1 -> enable pwm; if pwm==0, disable pwm, keep regulator enabled
29 2 -> enable pwm; if pwm==0, keep pwm and regulator enabled
30 3 -> enable pwm; if pwm==0, disable pwm and regulator
31 pwm1 rw relative speed (0-255), 255=max. speed.
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| /Documentation/devicetree/bindings/regulator/ |
| D | regulator.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liam Girdwood <lgirdwood@gmail.com>
11 - Mark Brown <broonie@kernel.org>
14 regulator-name:
18 regulator-min-microvolt:
21 regulator-max-microvolt:
24 regulator-microvolt-offset:
28 regulator-min-microamp:
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | sprd,pinctrl.txt | 9 driving level": One pin can output 3.0v or 1.8v, depending on the
11 select 3.0v, then the pin can output 3.0v. "system control" is used
15 There are too much various configuration that we can not list all
16 of them, so we can not make every Spreadtrum-special configuration
35 - input-enable
36 - input-disable
37 - output-high
38 - output-low
39 - bias-pull-up
40 - bias-pull-down
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| D | starfive,jh7110-sys-pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-sys-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
13 can be multiplexed and have configurable bias, drive strength,
18 any GPIO can be set up to be controlled by any of the peripherals.
21 - Jianlong Huang <jianlong.huang@starfivetech.com>
25 const: starfive,jh7110-sys-pinctrl
39 interrupt-controller: true
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| D | mediatek,mt8195-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8195-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
17 const: mediatek,mt8195-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
32 gpio-line-names: true
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| D | starfive,jh7110-aon-pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7110-aon-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Bindings for the JH7110 RISC-V SoC from StarFive Technology Ltd.
13 can be multiplexed and have configurable bias, drive strength,
18 - Jianlong Huang <jianlong.huang@starfivetech.com>
22 const: starfive,jh7110-aon-pinctrl
33 interrupt-controller: true
35 '#interrupt-cells':
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| D | mediatek,mt8188-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8188-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hui Liu <hui.liu@mediatek.com>
17 const: mediatek,mt8188-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
25 are defined in <dt-bindings/gpio/gpio.h>.
28 gpio-ranges:
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| D | mediatek,mt8186-pinctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8186-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
17 const: mediatek,mt8186-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
31 gpio-line-names: true
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| D | ti,da850-pupd.txt | 1 * Pin configuration for TI DA850/OMAP-L138/AM18x
4 Bias can only be selected for groups rather than individual pins.
8 - compatible: Must be "ti,da850-pupd"
9 - reg: Base address and length of the memory resource used by the pullup/down
17 - groups: An array of strings, each string containing the name of a pin group.
21 pinctrl-bindings.txt in this directory. The supported parameters are
22 bias-disable, bias-pull-up, bias-pull-down.
26 -------
30 pinconf: pin-controller@22c00c {
31 compatible = "ti,da850-pupd";
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| /Documentation/ABI/stable/ |
| D | sysfs-driver-firmware-zynqmp | 1 What: /sys/devices/platform/firmware\:zynqmp-firmware/ggs*
8 Global general storage register that can be used
11 The register is reset during system or power-on
17 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
18 # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
22 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
23 # echo 0x1234ABCD > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
27 What: /sys/devices/platform/firmware\:zynqmp-firmware/pggs*
35 can be used by system to pass information between
38 This register is only reset by the power-on reset
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| /Documentation/ABI/removed/ |
| D | sysfs-selinux-disable | 1 What: /sys/fs/selinux/disable
3 KernelVersion: 2.6.12-rc2 (predates git)
7 REMOVAL UPDATE: The SELinux runtime disable functionality was removed
10 The selinuxfs "disable" node allows SELinux to be disabled at runtime
15 parameter, but the selinuxfs "disable" node was created to make it
21 Thankfully, the need for the SELinux runtime disable appears to be
25 selinuxfs "disable" node and once that is complete we will start the
28 More information on /sys/fs/selinux/disable can be found under the
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| /Documentation/admin-guide/ |
| D | kernel-parameters.txt | 9 accept_memory=eager can be used to accept all memory
16 force -- enable ACPI if default was off
17 on -- enable ACPI but allow fallback to DT [arm64,riscv64]
18 off -- disable ACPI if default was on
19 noirq -- do not use ACPI for IRQ routing
20 strict -- Be less tolerant of platforms that are not
22 rsdt -- prefer RSDT over (default) XSDT
23 copy_dsdt -- copy DSDT to memory
24 nospcr -- disable console in ACPI SPCR table as
41 If set to vendor, prefer vendor-specific driver
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| /Documentation/ABI/testing/ |
| D | sysfs-driver-xdata | 1 What: /sys/class/misc/drivers/dw-xdata-pcie.<device>/write
6 will create write TLPs frames - from the Root Complex to the
7 Endpoint direction or to disable the PCIe traffic generator
10 Write y/1/on to enable, n/0/off to disable
13 echo 1 > /sys/class/misc/dw-xdata-pcie.<device>/write
15 echo 0 > /sys/class/misc/dw-xdata-pcie.<device>/write
17 The user can read the current PCIe link throughput generated
21 cat /sys/class/misc/dw-xdata-pcie.<device>/write
26 What: /sys/class/misc/dw-xdata-pcie.<device>/read
31 will create read TLPs frames - from the Endpoint to the Root
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| D | rtc-cdev | 4 Contact: linux-rtc@vger.kernel.org
6 The ioctl interface to drivers for real-time clocks (RTCs).
13 * RTC_AIE_ON, RTC_AIE_OFF: Enable or disable the alarm interrupt
17 RTCs that support alarms. Can be set upto 24 hours in the
22 powerful interface, which can issue alarms beyond 24 hours and
25 * RTC_PIE_ON, RTC_PIE_OFF: Enable or disable the periodic
28 * RTC_UIE_ON, RTC_UIE_OFF: Enable or disable the update
48 newer features -- including those enabled by ACPI -- are exposed
49 by the RTC class framework, but can't be supported by the older
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| D | sysfs-bus-iio-filter-admv8818 | 3 Contact: linux-iio@vger.kernel.org
5 Reading this returns the valid values that can be written to the
8 - auto -> Adjust bandpass filter to track changes in input clock rate.
9 - manual -> disable/unregister the clock rate notifier / input clock tracking.
10 - bypass -> bypass low pass filter, high pass filter and disable/unregister
15 Contact: linux-iio@vger.kernel.org
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| /Documentation/driver-api/crypto/iaa/ |
| D | iaa-crypto.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 The IAA hardware spec can be found here:
18 higher-level compression devices such as zswap.
20 Users can select IAA compress/decompress acceleration by specifying
24 For example, a zswap device can select the IAA 'fixed' mode
25 represented by selecting the 'deflate-iaa' crypto compression
28 # echo deflate-iaa > /sys/module/zswap/parameters/compressor
38 'deflate-iaa'. (Because the IAA hardware has a 4k history-window
52 Cryptographic API -> Hardware crypto devices -> Support for Intel(R) IAA Compression Accelerator
59 …Cryptographic API -> Hardware crypto devices -> Support for Intel(R) IAA Compression -> Enable Int…
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| /Documentation/driver-api/nvdimm/ |
| D | security.rst | 6 ---------------
10 security DSMs: "get security state", "set passphrase", "disable passphrase",
16 ------------------
28 update <old_keyid> <new_keyid> - enable or update passphrase.
29 disable <keyid> - disable enabled security and remove key.
30 freeze - freeze changing of security states.
31 erase <keyid> - delete existing user encryption key.
32 overwrite <keyid> - wipe the entire nvdimm.
33 master_update <keyid> <new_keyid> - enable or update master passphrase.
34 master_erase <keyid> - delete existing user encryption key.
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| /Documentation/admin-guide/hw-vuln/ |
| D | gather_data_sampling.rst | 1 .. SPDX-License-Identifier: GPL-2.0
3 GDS - Gather Data Sampling
10 -------
17 attacks. GDS is a purely sampling-based attack.
24 Because the buffers are shared between Hyper-Threads cross Hyper-Thread attacks
28 ----------------
29 Without mitigation, GDS can infer stale data across virtually all
32 Non-enclaves can infer SGX enclave data
33 Userspace can infer kernel data
34 Guests can infer data from hosts
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| /Documentation/devicetree/bindings/usb/ |
| D | snps,dwc3.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
13 This is usually a subnode to DWC3 glue to which it is connected, but can also
14 be presented as a standalone DT node with an optional vendor-specific
18 - $ref: usb-drd.yaml#
19 - if:
25 - dr_mode
29 $ref: usb-xhci.yaml#
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| /Documentation/trace/coresight/ |
| D | coresight-cpu-debug.rst | 9 ------------
11 Coresight CPU debug module is defined in ARMv8-a architecture reference manual
12 (ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate
13 debug module and it is mainly used for two modes: self-hosted debug and
15 debugger connects with SoC from JTAG port; on the other hand the program can
16 explore debugging method which rely on self-hosted debug mode, this document
19 The debug module provides sample-based profiling extension, which can be used
21 every CPU has one dedicated debug module to be connected. Based on self-hosted
22 debug mechanism, Linux kernel can access these related registers from mmio
29 --------------
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| /Documentation/fb/ |
| D | viafb.rst | 6 --------
15 ---------------
34 ----------------------
47 - 640x480 (default)
48 - 720x480
49 - 800x600
50 - 1024x768
53 - 8, 16, 32 (default:32)
56 - 60, 75, 85, 100, 120 (default:60)
59 - 0 : expansion (default)
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| /Documentation/devicetree/bindings/iio/frequency/ |
| D | adi,adrf6780.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
21 - adi,adrf6780
26 spi-max-frequency:
34 clock-names:
36 - const: lo_in
38 clock-output-names:
41 adi,vga-buff-en:
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| /Documentation/PCI/ |
| D | pci-iov-howto.rst | 1 .. SPDX-License-Identifier: GPL-2.0
9 :Authors: - Yu Zhao <yu.zhao@intel.com>
10 - Donald Dutile <ddutile@redhat.com>
15 What is SR-IOV
16 --------------
18 Single Root I/O Virtualization (SR-IOV) is a PCI Express Extended
22 Allocation of the VF can be dynamically controlled by the PF via
25 turned on, each VF's PCI configuration space can be accessed by its own
28 operates on the register set so it can be functional and appear as a
34 How can I enable SR-IOV capability
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| D | msi-howto.rst | 1 .. SPDX-License-Identifier: GPL-2.0
17 to change your driver to use MSI or MSI-X and some basic diagnostics to
28 in PCI 3.0 to allow each interrupt to be masked individually. The MSI-X
32 Devices may support both MSI and MSI-X, but only one can be enabled at
39 There are three reasons why using MSIs can give an advantage over
40 traditional pin-based interrupts.
42 Pin-based PCI interrupts are often shared amongst several devices.
47 When a device writes data to memory, then raises a pin-based interrupt,
49 arrived in memory (this becomes more likely with devices behind PCI-PCI
54 Using MSIs avoids this problem as the interrupt-generating write cannot
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