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/Documentation/security/tpm/
Dtpm-security.rst1 .. SPDX-License-Identifier: GPL-2.0-only
12 ------------
22 -----------------------------------------------
25 interposer which is a simple external device that can be installed in
34 try to insure that if we can't prevent the attack then at least we can
38 reset capability can be controlled by an attacker who has access to
42 ---------------------------
44 Since the attacker can send their own commands to the TPM, they can
60 The first can be thwarted by always doing HMAC protection of the PCR
63 response. However, the second can only really be detected by relying
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/Documentation/virt/
Dne_overview.rst1 .. SPDX-License-Identifier: GPL-2.0
15 can be separated from other applications running in the same VM. This
16 application then runs in a separate VM than the primary VM, namely an enclave.
24 carved out of the primary VM. Each enclave is mapped to a process running in the
25 primary VM, that communicates with the NE kernel driver via an ioctl interface.
29 1. An enclave abstraction process - a user space process running in the primary
33 There is a NE emulated PCI device exposed to the primary VM. The driver for this
39 hypervisor running on the host where the primary VM is running. The Nitro
42 2. The enclave itself - a VM running on the same host as the primary VM that
43 spawned it. Memory and CPUs are carved out of the primary VM and are dedicated
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/Documentation/devicetree/bindings/net/can/
Dst,stm32-bxcan.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/st,stm32-bxcan.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
9 description: STMicroelectronics BxCAN controller for CAN bus
12 - Dario Binacchi <dario.binacchi@amarulasolutions.com>
15 - $ref: can-controller.yaml#
20 - st,stm32f4-bxcan
22 st,can-primary:
24 Primary mode of the bxCAN peripheral is only relevant if the chip has
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/Documentation/gpu/amdgpu/display/
Dmpo-overview.rst6 'Documentation/gpu/amdgpu/display/dcn-overview.rst'.
10 fixed-function hardware in the display controller rather than using graphics or
11 compute shaders for composition. This can yield some power savings if it means
12 the graphics/compute pipelines can be put into low-power states. In summary,
13 MPO can bring the following benefits:
15 * Decreased GPU and CPU workload - no composition shaders needed, no extra
16 buffer copy needed, GPU can remain idle.
17 * Plane independent page flips - No need to be tied to global compositor
18 page-flip present rate, reduced latency, independent timing.
20 .. note:: Keep in mind that MPO is all about power-saving; if you want to learn
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/Documentation/arch/sparc/oradax/
Ddax-hv-api.txt3 Publication date 2017-09-25 08:21
5 Extracted via "pdftotext -f 547 -l 572 -layout sun4v_20170925.pdf"
16 live-migration and other system management activities.
20 …high speed processoring of database-centric operations. The coprocessors may support one or more of
28 …e Completion Area and, unless execution order is specifically restricted through the use of serial-
39 …machine, however, internal resource limitations within the virtual machine can cause CCB submissio…
45 …device node in the guest MD (Section 8.24.17, “Database Analytics Accelerators (DAX) virtual-device
51 36.1.1.1. "ORCL,sun4v-dax" Device Compatibility
54 • No-op/Sync
81 36.1.1.2. "ORCL,sun4v-dax-fc" Device Compatibility
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Doracle-dax.rst7 as well as physical memory. It can perform several operations on data
25 the accompanying document, dax-hv-api.txt, which is a plain text
27 Specification" version 3.0.20+15, dated 2017-09-25.
64 domain (LDOM) can have a partition of physical memory that is isolated
69 The DAX coprocessor can only operate on physical memory, so before a
70 request can be fed to the coprocessor, all the addresses in a CCB must
86 made accessible via mmap(), and are read-only for the application.
105 name can be used to determine what the platform supports.
109 equal to the number of bytes given in the call. Otherwise -1 is
113 -----------
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/Documentation/devicetree/bindings/interrupt-controller/
Dsnps,dw-apb-ictl.txt5 APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt
9 - compatible: shall be "snps,dw-apb-ictl"
10 - reg: physical base address of the controller and length of memory mapped
12 - interrupt-controller: identifies the node as an interrupt controller
13 - #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
16 - interrupts: interrupt reference to primary interrupt controller
20 - 0 maps to bit 0 of low interrupts,
21 - 1 maps to bit 1 of low interrupts,
22 - 32 maps to bit 0 of high interrupts,
23 - 33 maps to bit 1 of high interrupts,
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Dti,omap-intc-irq.txt3 On TI omap2 and 3 the intc interrupt controller can provide
7 - compatible: should be one of
8 "ti,omap2-intc"
9 "ti,omap3-intc"
10 "ti,dm814-intc"
11 "ti,dm816-intc"
12 "ti,am33xx-intc"
14 - interrupt-controller : Identifies the node as an interrupt controller
15 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
17 - interrupts: interrupt reference to primary interrupt controller
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Dti,keystone-irq.txt3 On Keystone SOCs, DSP cores can send interrupts to ARM
5 The IRQ handler running on HOST OS can identify DSP signal source by
10 - compatible: should be "ti,keystone-irq"
11 - ti,syscon-dev : phandle and offset pair. The phandle to syscon used to
14 - interrupt-controller : Identifies the node as an interrupt controller
15 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
17 - interrupts: interrupt reference to primary interrupt controller
24 compatible = "ti,keystone-irq";
25 ti,syscon-dev = <&devctrl 0x2a0>;
27 interrupt-controller;
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/Documentation/devicetree/bindings/powerpc/fsl/
Dmsi-pic.txt4 - compatible : compatible list, may contain one or two entries
5 The first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
6 etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or
7 "fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic
9 provided to access these 16 registers, and compatible "fsl,mpic-msi-v4.3"
13 - reg : It may contain one or two regions. The first region should contain
19 - interrupts : each one of the interrupts here is one entry per 32 MSIs,
21 be set as edge sensitive. If msi-available-ranges is present, only
25 - msi-available-ranges: use <start count> style section to define which
26 msi interrupt can be used in the 256 msi interrupts. This property is
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/Documentation/userspace-api/media/v4l/
Dvidioc-g-tuner.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
13 VIDIOC_G_TUNER - VIDIOC_S_TUNER - Get or set tuner attributes
52 Since this is a write-only ioctl, it does not return the actually
68 .. flat-table:: struct v4l2_tuner
69 :header-rows: 0
70 :stub-columns: 0
72 * - __u32
73 - ``index``
74 - :cspan:`1` Identifies the tuner, set by the application.
75 * - __u8
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/Documentation/arch/powerpc/
Dassociativity.rst9 are represented as being members of a sub-grouping domain. This performance
17 Hypervisor indicates the type/form of associativity used via "ibm,architecture-vec-5 property".
18 Bit 0 of byte 5 in the "ibm,architecture-vec-5" property indicates usage of Form 0 or Form 1.
20 bit 2 of byte 5 in the "ibm,architecture-vec-5" property is used.
23 ------
27 ------
28 With Form 1 a combination of ibm,associativity-reference-points, and ibm,associativity
34 The “ibm,associativity-reference-points” property contains a list of one or more numbers
39 { primary domainID index, secondary domainID index, tertiary domainID index.. }
41 Linux kernel uses the domainID at the primary domainID index as the NUMA node id.
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/Documentation/PCI/endpoint/
Dpci-ntb-howto.rst1 .. SPDX-License-Identifier: GPL-2.0
4 PCI Non-Transparent Bridge (NTB) Endpoint Function (EPF) User Guide
9 This document is a guide to help users use pci-epf-ntb function driver
13 Documentation/PCI/endpoint/pci-ntb-function.rst
19 ---------------------------
27 2900000.pcie-ep 2910000.pcie-ep
32 2900000.pcie-ep 2910000.pcie-ep
36 -------------------------
40 # ls /sys/bus/pci-epf/drivers
49 Creating pci-epf-ntb Device
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Dpci-endpoint-cfs.rst1 .. SPDX-License-Identifier: GPL-2.0
18 directory. configfs can be mounted using the following command::
20 mount -t configfs none /sys/kernel/config
54 Every <EPF device> directory consists of the following entries that can be
73 ... primary/
79 Non-transparent bridge), symlink of endpoint controller connected to primary
80 interface should be added in 'primary' directory and symlink of endpoint
84 The <EPF Device> directory can have a list of symbolic links
111 that represents a physical function can be linked to a EPC device.
138 [1] Documentation/PCI/endpoint/pci-endpoint.rst
/Documentation/devicetree/bindings/remoteproc/
Dst-rproc.txt1 STMicroelectronics Co-Processor Bindings
2 ----------------------------------------
6 Co-processors can be controlled from the bootloader or the primary OS. If
7 the bootloader starts a co-processor, the primary OS must detect its state
11 - compatible Should be one of:
12 "st,st231-rproc"
13 "st,st40-rproc"
14 - memory-region Reserved memory (See: ../reserved-memory/reserved-memory.txt)
15 - resets Reset lines (See: ../reset/reset.txt)
16 - reset-names Must be "sw_reset" and "pwr_reset"
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/Documentation/usb/
Ddwc3.rst11 - Convert interrupt handler to per-ep-thread-irq
13 As it turns out some DWC3-commands ~1ms to complete. Currently we spin
18 - dwc core implements a demultiplexing irq chip for interrupts per
20 to the device. If MSI provides per-endpoint interrupt this dummy
21 interrupt chip can be replaced with "real" interrupts.
22 - interrupts are requested / allocated on usb_ep_enable() and removed on
25 - dwc3_send_gadget_ep_cmd() will sleep in wait_for_completion_timeout()
27 - the interrupt handler is split into the following pieces:
29 - primary handler of the device
34 - threaded handler of the device
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/Documentation/mm/
Dpage_cache.rst1 .. SPDX-License-Identifier: GPL-2.0
7 The page cache is the primary way that the user and the rest of the kernel
8 interact with filesystems. It can be bypassed (e.g. with O_DIRECT),
/Documentation/devicetree/bindings/media/
Drenesas,drif.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Gen3 Digital Radio Interface Controller (DRIF)
10 - Ramesh Shanmugasundaram <rashanmu@gmail.com>
11 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
14 R-Car Gen3 DRIF is a SPI like receive only slave device. A general
17 +---------------------+ +---------------------+
18 | |-----SCK------->|CLK |
19 | Master |-----SS-------->|SYNC DRIFn (slave) |
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/Documentation/ABI/testing/
Dsysfs-class-tee4 Contact: op-tee@lists.trustedfirmware.org
6 RPMB frames can be routed to the RPMB device via the
7 user-space daemon tee-supplicant or the RPMB subsystem
11 subsystem without assistance from tee-supplicant. It
13 space if the variable is absent. The primary purpose
15 tee-supplicant is needed in the early boot with initramfs.
/Documentation/devicetree/bindings/display/
Dmipi-dsi-bus.txt8 This document describes DSI bus-specific properties only or defines existing
25 - #address-cells: The number of cells required to represent an address on the
26 bus. DSI peripherals are addressed using a 2-bit virtual channel number, so
27 a maximum of 4 devices can be addressed on a single bus. Hence the value of
29 - #size-cells: Should be 0. There are cases where it makes sense to use a
33 - clock-master: boolean. Should be enabled if the host is being used in
43 ------------------------------------------------------
45 Peripherals with the DSI bus as the primary control bus, or peripherals with
49 device-specific properties.
52 - reg: The virtual channel number of a DSI peripheral. Must be in the range
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/Documentation/admin-guide/device-mapper/
Ddm-zoned.rst2 dm-zoned
5 The dm-zoned device mapper target exposes a zoned block device (ZBC and
7 pattern constraints. In effect, it implements a drive-managed zoned
10 host-managed zoned block devices and can mitigate the potential
11 device-side performance degradation due to excessive random writes on
12 host-aware zoned block devices.
21 http://www.t13.org/Documents/UploadedDocuments/docs2015/di537r05-Zoned_Device_ATA_Command_Set_ZAC.p…
23 The dm-zoned implementation is simple and minimizes system overhead (CPU
25 host-managed disk with 256 MB zones, dm-zoned memory usage per disk
29 dm-zoned target devices are formatted and checked using the dmzadm
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/Documentation/admin-guide/cgroup-v1/
Drdma.rst8 1-1. What is RDMA controller?
9 1-2. Why RDMA controller needed?
10 1-3. How is RDMA controller implemented?
16 1-1. What is RDMA controller?
17 -----------------------------
20 set of processes can use. These processes are grouped using RDMA controller.
22 RDMA controller defines two resources which can be limited for processes of a
25 1-2. Why RDMA controller needed?
26 --------------------------------
28 Currently user space applications can easily take away all the rdma verb
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/Documentation/devicetree/bindings/pinctrl/
Dpinctrl-palmas.txt3 The pins of Palmas device can be set on different option and provides
7 - compatible: It must be one of following:
8 - "ti,palmas-pinctrl" for Palma series of the pincontrol.
9 - "ti,tps65913-pinctrl" for Palma series device TPS65913.
10 - "ti,tps80036-pinctrl" for Palma series device TPS80036.
12 Please refer to pinctrl-bindings.txt in this directory for details of the
18 list of pins. This configuration can include the mux function to select on
19 those pin(s), and various pin configuration parameters, such as pull-up,
32 - ti,palmas-enable-dvfs1: Enable DVFS1. Configure pins for DVFS1 mode.
33 Selection primary or secondary function associated to I2C2_SCL_SCE,
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/Documentation/networking/
Dmulti-pf-netdev.rst1 .. SPDX-License-Identifier: GPL-2.0
5 Multi-PF Netdev
11 - `Background`_
12 - `Overview`_
13 - `mlx5 implementation`_
14 - `Channels distribution`_
15 - `Observability`_
16 - `Steering`_
17 - `Mutually exclusive features`_
22 The Multi-PF NIC technology enables several CPUs within a multi-socket server to connect directly to
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/Documentation/admin-guide/hw-vuln/
Dprocessor_mmio_stale_data.rst5 Processor MMIO Stale Data Vulnerabilities are a class of memory-mapped I/O
6 (MMIO) vulnerabilities that can expose data. The sequences of operations for
12 stale data into core fill buffers where the data can subsequently be inferred
24 read into an architectural, software-visible state or sampled from a buffer or
28 -----------------------------------------
29 Stale data may propagate from fill buffers (FB) into the non-coherent portion
30 of the uncore on some non-coherent writes. Fill buffer propagation by itself
35 -------------------------------------
38 shared by all client cores. For non-coherent reads that go to sideband
44 Primary Stale Data Propagator (PSDP)
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