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/Documentation/devicetree/bindings/net/can/
Dcan-transceiver.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/can/can-transceiver.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CAN transceiver
9 description: CAN transceiver generic properties bindings
12 - Rob Herring <robh@kernel.org>
15 max-bitrate:
17 description: a positive non 0 value that determines the max speed that CAN/CAN-FD can run.
Dbosch,m_can.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/can/bosch,m_can.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
9 description: Bosch MCAN controller for CAN bus
12 - Chandrasekar Ramakrishnan <rcsekar@samsung.com>
15 - $ref: can-controller.yaml#
23 - description: M_CAN registers map
24 - description: message RAM
26 reg-names:
[all …]
Dfsl,flexcan.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/fsl,flexcan.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Flexcan CAN controller on Freescale's ARM and PowerPC system-on-a-chip (SOC).
11 - Marc Kleine-Budde <mkl@pengutronix.de>
14 - $ref: can-controller.yaml#
19 - enum:
20 - fsl,imx95-flexcan
21 - fsl,imx93-flexcan
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Dholt_hi311x.txt1 * Holt HI-311X stand-alone CAN controller device tree bindings
4 - compatible: Should be one of the following:
5 - "holt,hi3110" for HI-3110
6 - reg: SPI chip select.
7 - clocks: The clock feeding the CAN controller.
8 - interrupts: Should contain IRQ line for the CAN controller.
11 - vdd-supply: Regulator that powers the CAN controller.
12 - xceiver-supply: Regulator that powers the CAN transceiver.
15 can0: can@1 {
19 interrupt-parent = <&gpio4>;
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Dti_hecc.txt1 Texas Instruments High End CAN Controller (HECC)
8 - compatible: "ti,am3517-hecc"
9 - reg: addresses and lengths of the register spaces for 'hecc', 'hecc-ram'
11 - reg-names :"hecc", "hecc-ram", "mbx"
12 - interrupts: interrupt mapping for the hecc interrupts sources
13 - clocks: clock phandles (see clock bindings for details)
16 - ti,use-hecc1int: if provided configures HECC to produce all interrupts
19 - xceiver-supply: regulator that powers the CAN transceiver
24 hecc: can@5c050000 {
25 compatible = "ti,am3517-hecc";
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Dmicrochip,mcp2510.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/can/microchip,mcp2510.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip MCP251X stand-alone CAN controller
10 - Marc Kleine-Budde <mkl@pengutronix.de>
15 - microchip,mcp2510
16 - microchip,mcp2515
17 - microchip,mcp25625
28 vdd-supply:
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Dmicrochip,mcp251xfd.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/can/microchip,mcp251xfd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip MCP2517FD, MCP2518FD and MCP251863 stand-alone CAN controller
10 - Marc Kleine-Budde <mkl@pengutronix.de>
13 - $ref: can-controller.yaml#
18 - enum:
19 - microchip,mcp2517fd
20 - microchip,mcp2518fd
[all …]
/Documentation/devicetree/bindings/phy/
Dti,tcan104x-can.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/ti,tcan104x-can.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TCAN104x CAN TRANSCEIVER PHY
10 - Aswath Govindraju <a-govindraju@ti.com>
14 pattern: "^can-phy"
18 - nxp,tjr1443
19 - ti,tcan1042
20 - ti,tcan1043
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Dxlnx,zynqmp-psgtr.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/xlnx,zynqmp-psgtr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx ZynqMP Gigabit Transceiver PHY
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 This binding describes the Xilinx ZynqMP Gigabit Transceiver (GTR) PHY. The
18 "#phy-cells":
23 - description: The GTR lane
26 - description: The PHY type
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Dqcom,usb-snps-femto-v2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,usb-snps-femto-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Synopsys Femto High-Speed USB PHY V2
10 - Wesley Cheng <quic_wcheng@quicinc.com>
13 Qualcomm High-Speed USB PHY
18 - items:
19 - enum:
20 - qcom,sa8775p-usb-hs-phy
[all …]
/Documentation/networking/device_drivers/ethernet/3com/
D3c509.rst1 .. SPDX-License-Identifier: GPL-2.0
21 ethercards in Linux. These cards are commonly known by the most widely-used
22 card's 3Com model number, 3c509. They are all 10mb/s ISA-bus cards and shouldn't
23 be (but sometimes are) confused with the similarly-numbered PCI-bus "3c905"
28 - 3c509 (original ISA card)
29 - 3c509B (later revision of the ISA card; supports full-duplex)
30 - 3c589 (PCMCIA)
31 - 3c589B (later revision of the 3c589; supports full-duplex)
32 - 3c579 (EISA)
45 The driver allows boot- or load-time overriding of the card's detected IOADDR,
[all …]
/Documentation/devicetree/bindings/sound/
Dapple,mca.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple MCA I2S transceiver
10 MCA is an I2S transceiver peripheral found on M1 and other Apple chips. It is
11 composed of a number of identical clusters which can operate independently
15 - Martin Povišer <povik+lin@cutebit.org>
18 - $ref: dai-common.yaml#
23 - enum:
24 - apple,t6000-mca
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/Documentation/devicetree/bindings/serial/
Drs485.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 direction for the built-in half-duplex mode. The properties described
11 hereafter shall be given to a half-duplex capable UART node.
14 - Rob Herring <robh@kernel.org>
17 rs485-rts-delay:
18 description: prop-encoded-array <a b>
19 $ref: /schemas/types.yaml#/definitions/uint32-array
21 - description: Delay between rts signal and beginning of data sent in
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/Documentation/devicetree/bindings/display/
Damlogic,meson-vpu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
17 DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
19 D |-------| |----| | | | | HDMI PLL |
20 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
21 R |-------| |----| Processing | | | | |
22 | osd2 | | | |---| Enci ----------|----|-----VDAC------|
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/Documentation/driver-api/usb/
Dwriting_musb_glue_layer.rst15 Instead, these embedded UDC rely on the USB On-the-Go (OTG)
18 Dual-Role Controller (MUSB HDRC) found in the Mentor Graphics Inventra™
21 As a self-taught exercise I have written an MUSB glue layer for the
23 kernel source tree. This layer can be found at
28 .. _musb-basics:
33 To get started on the topic, please read USB On-the-Go Basics (see
46 ------------------------
47 | | <------- drivers/usb/gadget
48 | Linux USB Core Stack | <------- drivers/usb/host
49 | | <------- drivers/usb/core
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/Documentation/devicetree/bindings/net/
Dti,dp83822.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Andrew Davis <afd@ti.com>
14 The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
16 data over standard, twisted-pair cables or to connect to an external,
17 fiber-optic transceiver. Additionally, the DP83822 provides flexibility to
20 Specifications about the Ethernet PHY can be found at:
24 - $ref: ethernet-phy.yaml#
30 ti,link-loss-low:
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Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
[all …]
Dsff,sfp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Small Form Factor (SFF) Committee Small Form-factor Pluggable (SFP)
8 Transceiver
11 - Russell King <linux@armlinux.org.uk>
16 - sff,sfp # for SFP modules
17 - sff,sff # for soldered down SFF modules
19 i2c-bus:
24 maximum-power-milliwatt:
[all …]
Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
27 Specifications about the Ethernet PHY can be found at:
34 nvmem-cells:
40 nvmem-cell-names:
[all …]
/Documentation/driver-api/gpio/
Dintro.rst17 A "General Purpose Input/Output" (GPIO) is a flexible software-controlled
22 which GPIOs. Drivers can be written generically, so that board setup code
25 System-on-Chip (SOC) processors heavily rely on GPIOs. In some cases, every
26 non-dedicated pin can be configured as a GPIO; and most chips have at least
27 several dozen of them. Programmable logic devices (like FPGAs) can easily
31 Most PC southbridges have a few dozen GPIO-capable pins (with only the BIOS
36 - Output values are writable (high=1, low=0). Some chips also have
38 value might be driven, supporting "wire-OR" and similar schemes for the
41 - Input values are likewise readable (1, 0). Some chips support readback
42 of pins configured as "output", which is very useful in such "wire-OR"
[all …]
/Documentation/driver-api/serial/
Dserial-rs485.rst8 EIA-485, also known as TIA/EIA-485 or RS-485, is a standard defining the
12 because it can be used effectively over long distances and in electrically
15 2. Hardware-related Considerations
18 Some CPUs/UARTs (e.g., Atmel AT91 or 16C950 UART) contain a built-in
19 half-duplex mode capable of automatically controlling line direction by
20 toggling RTS or DTR signals. That can be used to control external
21 half-duplex hardware like an RS485 transceiver or any RS232-connected
22 half-duplex devices like some modems.
26 available at user-level to allow switching from one mode to the other, and
36 The device tree can also provide RS485 boot time parameters
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/Documentation/networking/
Dethtool-netlink.rst19 Requests can be divided into three categories: "get" (retrieving information),
27 wake-on-lan password) omitted.
34 can distinguish three states: "on", "off" and "not present" (meaning the
37 number 1 but any non-zero value should be understood as "true" by recipient.
41 with "+", parent nest can contain multiple attributes of the same type. This
44 Attributes that need to be filled-in by device drivers and that are dumped to
87 there may be more than one PHY on the link, the PHY index can be passed in the
98 representing bit values and mask of affected bits) and bit-by-bit (list of
101 Verbose (bit-by-bit) bitsets allow sending symbolic names for bits together
110 A bitset can represent either a value/mask pair (``ETHTOOL_A_BITSET_NOMASK``
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/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/
Dcounters.rst1 .. SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
13 - `Overview`_
14 - `Groups`_
15 - `Types`_
16 - `Descriptions`_
27 ----------------------------------------
29 ---------------------------------------- ---------------------------------------- |
32 | ------------------- --------------- | | ------------------- --------------- | |
34 | ------------------- --------------- | | ------------------- --------------- | |
36 | ------------------- | | ------------------- | |
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/Documentation/devicetree/bindings/mfd/
Dti,twl.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andreas Kemnade <andreas@kemnade.info>
15 USB transceiver or Audio amplifier.
19 - if:
26 "^regulator-":
30 - ti,twl4030-vaux1
31 - ti,twl4030-vaux2
32 - ti,twl4030-vaux3
[all …]
/Documentation/networking/device_drivers/ethernet/aquantia/
Datlantic.rst1 .. SPDX-License-Identifier: GPL-2.0
8 For the aQuantia Multi-Gigabit PCI Express Family of Ethernet Adapters
12 - Identifying Your Adapter
13 - Configuration
14 - Supported ethtool options
15 - Command Line Parameters
16 - Config file parameters
17 - Support
18 - License
23 The driver in this release is compatible with AQC-100, AQC-107, AQC-108
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