Searched full:can1 (Results 1 – 15 of 15) sorted by relevance
| /Documentation/devicetree/bindings/net/can/ |
| D | st,stm32-bxcan.yaml | 69 SRAM memory shared by the two bxCAN cells (CAN1 primary and CAN2
87 can1: can@40006400 {
92 resets = <&rcc STM32F4_APB1_RESET(CAN1)>;
93 clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
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| D | renesas,rcar-canfd.yaml | 126 - description: CAN1 error interrupt
127 - description: CAN1 transmit interrupt
128 - description: CAN1 transmit/receive FIFO receive completion interrupt
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| D | allwinner,sun4i-a10-can.yaml | 72 can1: can@1c2bc00 {
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| /Documentation/devicetree/bindings/reset/ |
| D | zynq-reset.txt | 46 257: can1 reset
48 259: can1 ref reset
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | loongson,ls2k-pinctrl.yaml | 42 enum: [gpio, sdio, can1, can0, pwm3, pwm2, pwm1, pwm0, i2c1, i2c0,
47 enum: [gpio, sdio, can1, can0, pwm3, pwm2, pwm1, pwm0, i2c1, i2c0,
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| D | pinctrl_spear.txt | 140 "can0", "can1", "pwm0_1", "pwm2", "pwm3", "ssp1", "ssp2", "mii2",
149 "i2c_4_5", "i2c_6_7", "can0", "can1", "pci", "sata", "ssp1", "gpt64"
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| D | brcm,cygnus-pinmux.txt | 120 "can1": "can1_grp"
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| D | nvidia,tegra234-pinmux-common.yaml | 17 enum: [ gp, uartc, i2c8, spi2, i2c2, can1, can0, rsvd0, eth0, eth2,
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| D | xlnx,pinctrl-zynq.yaml | 116 can1, uart0, uart1, i2c0, i2c1, ttc0, ttc1, swdt0, gpio0,
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| D | nvidia,tegra194-pinmux.yaml | 33 enum: [ aud, can0, can1, ccla, dca, dcb, dgpu, directdc, directdc1,
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| D | xlnx,zynqmp-pinctrl.yaml | 235 sdio1_cd, nand0, nand0_ce, nand0_rb, nand0_dqs, can0, can1, uart0, uart1,
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| /Documentation/devicetree/bindings/clock/ |
| D | zynq-7000.txt | 61 20: can1
99 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
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| D | imx28-clock.yaml | 78 can1 59
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| /Documentation/devicetree/bindings/soc/mobileye/ |
| D | mobileye,eyeq5-olb.yaml | 67 timer0, timer1, timer2, timer5, uart0, uart1, can0, can1, spi0,
154 const: can1
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| /Documentation/admin-guide/ |
| D | devices.txt | 1565 1 = /dev/can1 Second CAN-Bus controller
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