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/Documentation/devicetree/bindings/sound/
Dxlnx,i2s.txt1 Device-Tree bindings for Xilinx I2S PL block
3 The IP supports I2S based playback/capture audio
6 - compatible: "xlnx,i2s-transmitter-1.0" for playback and
7 "xlnx,i2s-receiver-1.0" for capture
9 Required property common to both I2S playback and capture:
10 - reg: Base address and size of the IP core instance.
11 - xlnx,dwidth: sample data width. Can be any of 16, 24.
12 - xlnx,num-channels: Number of I2S streams. Can be any of 1, 2, 3, 4.
13 supported channels = 2 * xlnx,num-channels
18 compatible = "xlnx,i2s-receiver-1.0";
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Drockchip-i2s.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/rockchip-i2s.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The I2S bus (Inter-IC sound bus) is a serial link for digital
14 - Heiko Stuebner <heiko@sntech.de>
17 - $ref: dai-common.yaml#
22 - const: rockchip,rk3066-i2s
23 - items:
24 - enum:
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Dfsl,ssi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
13 Notes on fsl,playback-dma and fsl,capture-dma
14 On SOCs that have an SSI, specific DMA channels are hard-wired for playback
15 and capture. On the MPC8610, for example, SSI1 must use DMA channel 0 for
16 playback and DMA channel 1 for capture. SSI2 must use DMA channel 2 for
17 playback and DMA channel 3 for capture. The developer can choose which
18 DMA controller to use, but the channels themselves are hard-wired. The
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Dadi,axi-i2s.txt1 ADI AXI-I2S controller
4 (capture) or both directions enabled.
7 - compatible : Must be "adi,axi-i2s-1.00.a"
8 - reg : Must contain I2S core's registers location and length
9 - clocks : Pairs of phandle and specifier referencing the controller's clocks.
12 - clock-names : "axi" for the clock to the AXI interface, "ref" for the sample
14 - dmas: Pairs of phandle and specifier for the DMA channels that are used by
15 the core. The core expects two dma channels if both transmit and receive are
17 - dma-names : "tx" for the transmit channel, "rx" for the receive channel.
19 For more details on the 'dma', 'dma-names', 'clock' and 'clock-names' properties
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/Documentation/ABI/testing/
Dconfigfs-usb-gadget-uac11 What: /config/usb-gadget/gadget/functions/uac1.name
8 c_chmask capture channel mask
9 c_srate list of capture sampling rates (comma-separated)
10 c_ssize capture sample size (bytes)
11 c_mute_present capture mute control enable
12 c_volume_present capture volume control enable
13 c_volume_min capture volume control min value
15 c_volume_max capture volume control max value
17 c_volume_res capture volume control resolution
20 p_srate list of playback sampling rates (comma-separated)
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Dsysfs-class-pwm6 The pwm/ class sub-directory belongs to the Generic PWM
8 channels.
24 The number of PWM channels supported by the PWM chip.
32 Value is between 0 and /sys/class/pwm/pwmchipN/npwm - 1.
81 What: /sys/class/pwm/pwmchip<N>/pwmX/capture
86 Capture information about a PWM signal. The output format is a
/Documentation/devicetree/bindings/pwm/
Dpwm-st.txt2 --------------------------------------
5 - compatible : "st,pwm"
6 - #pwm-cells : Number of cells used to specify a PWM. First cell
7 specifies the per-chip index of the PWM to use and the
8 second cell is the period in nanoseconds - fixed to 2
10 - reg : Physical base address and length of the controller's
12 - pinctrl-names: Set to "default".
13 - pinctrl-0: List of phandles pointing to pin configuration nodes
16 - clock-names: Valid entries are "pwm" and/or "capture".
17 - clocks: phandle of the clock used by the PWM module.
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/Documentation/sound/cards/
Demu-mixer.rst2 E-MU Digital Audio System mixer / default DSP code
5 This document covers the E-MU 0404/1010/1212/1616/1820 PCI/PCI-e/CardBus
9 alternative front-end geared towards semi-professional studio recording.
11 This document is based on audigy-mixer.rst.
17 The EMU10K2 chips have a very short capture FIFO, which makes recording
33 This driver supports only 16-bit 44.1/48 kHz operation. The multi-channel
34 device (see emu10k1-jack.rst) additionally supports 24-bit capture.
37 <https://github.com/ossilator/linux/tree/ossis-emu10k1>`_.
38 Its multi-channel device supports 24-bit for both playback and capture,
62 FX-bus
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Dcmipci.rst2 Brief Notes on C-Media 8338/8738/8768/8770 Driver
8 Front/Rear Multi-channel Playback
9 ---------------------------------
12 channels can be used for front/rear playbacks. Since there are two
13 DACs, both streams are handled independently unlike the 4/6ch multi-
22 - The first DAC supports U8 and S16LE formats, while the second DAC
24 - The second DAC supports only two channel stereo.
44 on and "double DAC" mode. Actually I could hear separate 4 channels
51 control switch in the driver "Line-In As Rear", which you can change
52 via alsamixer or somewhat else. When this switch is on, line-in jack
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Dmaya44.rst8 keep here as reference -- tiwai
22 … programming information, so I (Rainer Zimmermann) had to find out some card-specific information …
24 This is the first testing version of the Maya44 driver released to the alsa-devel mailing list (Feb…
29 - playback and capture at all sampling rates
30 - input/output level
31 - crossmixing
32 - line/mic switch
33 - phantom power switch
34 - analogue monitor a.k.a bypass
39 - Channel 3+4 analogue - S/PDIF input switching
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Demu10k1-jack.rst12 - Lee Revell, 2005.03.30
19 For those unfamiliar with kX ASIO, this consists of 16 capture and 16 playback
20 channels. With a post 2.6.9 Linux kernel, latencies down to 64 (1.33 ms) or
25 fairly self explanatory - select Duplex, then for capture and playback select
26 the multichannel devices, set the in and out channels to 16, and the sample
30 /usr/local/bin/jackd -R -dalsa -r48000 -p64 -n2 -D -Chw:0,2 -Phw:0,3 -S
36 sb-live-mixer.rst (or audigy-mixer.rst).
40 input channels have physical inputs connected to them depends on the card
49 still see 16 capture channels, but only 14 are available for recording inputs.
53 channels.
Daudiophile-usb.rst2 Guide to using M-Audio Audiophile USB with ALSA and Jack
9 This document is a guide to using the M-Audio Audiophile USB (tm) device with
15 * v1.4 - Thibault Le Meur (2007-07-11)
17 - Added Low Endianness nature of 16bits-modes
19 - Modifying document structure
21 * v1.5 - Thibault Le Meur (2007-07-12)
22 - Added AC3/DTS passthru info
35 - This port supports 2 pairs of line-level audio inputs (1/4" TS and RCA)
36 - When the 1/4" TS (jack) connectors are connected, the RCA connectors
57 * 16-bit/48kHz ==> 4 channels in + 4 channels out
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/Documentation/devicetree/bindings/media/
Dti,da850-vpif.txt2 ----------------------
5 capture and display on the DA850/AM18x family of TI DaVinci/Sitara
12 - compatible: must be "ti,da850-vpif"
13 - reg: physical base address and length of the registers set for the device;
14 - interrupts: should contain IRQ line for the VPIF
16 Video Capture:
18 VPIF has a 16-bit parallel bus input, supporting 2 8-bit channels or a
19 single 16-bit channel. It should contain one or two port child nodes
21 describe the input and port@1 output channels. Please refer to the
23 Documentation/devicetree/bindings/media/video-interfaces.txt.
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/Documentation/sound/designs/
Dcontrol-names.rst8 ---------------
17 Capture one direction
19 Bypass Capture one direction
33 <nothing> channel independent, or applies to all channels
34 Front front left/right channels
36 CLFE C/LFE channels
68 Headset Mic mic part of combined headset jack - 4-pin
70 Headphone Mic mic part of either/or - 3-pin headphone or mic
79 Analog Loopback D/A -> A/D loopback
80 Digital Loopback playback -> capture loopback -
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Doss-emulation.rst2 Notes on Kernel OSS-Emulation
13 as add-on kernel modules, snd-pcm-oss, snd-mixer-oss and snd-seq-oss.
18 is called. The alias is defined ``sound-service-x-y``, where x and y are
22 Only necessary step for auto-loading of OSS modules is to define the
25 alias sound-slot-0 snd-emu10k1
27 As the second card, define ``sound-slot-1`` as well.
29 ``alias sound-slot-0 snd-card-0`` doesn't work any more like the old
38 after the corresponding OSS-emulation module is loaded. Don't worry
79 snd-pcm-oss and snd-rawmidi. In the case of PCM, the following
80 options are available for snd-pcm-oss:
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/Documentation/devicetree/bindings/soc/microchip/
Datmel,at91rm9200-tcb.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
14 timer has three channels with two counters each.
19 - enum:
20 - atmel,at91rm9200-tcb
21 - atmel,at91sam9x5-tcb
22 - atmel,sama5d2-tcb
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/Documentation/admin-guide/media/
Dimx.rst1 .. SPDX-License-Identifier: GPL-2.0
3 i.MX Video Capture Driver
7 ------------
10 handles the flow of image frames to and from capture devices and
13 For image capture, the IPU contains the following internal subunits:
15 - Image DMA Controller (IDMAC)
16 - Camera Serial Interface (CSI)
17 - Image Converter (IC)
18 - Sensor Multi-FIFO Controller (SMFC)
19 - Image Rotator (IRT)
[all …]
Draspberrypi-pisp-be.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Raspberry Pi PiSP Back End Memory-to-Memory ISP (pisp-be)
10 The PiSP Back End is a memory-to-memory Image Signal Processor (ISP) which reads
13 pixel data back to memory through two distinct output channels.
19 tessellation and the computation of low-level configuration parameters is
24 an image sensor through a MIPI CSI-2 compatible capture interface, storing them
29 The pisp-be driver
32 The Raspberry Pi PiSP Back End (pisp-be) driver is located under
33 drivers/media/platform/raspberrypi/pisp-be. It uses the `V4L2 API` to register
34 a number of video capture and output devices, the `V4L2 subdev API` to register
[all …]
/Documentation/driver-api/iio/
Dbuffers.rst11 The Industrial I/O core offers a way for continuous data capture based on a
12 trigger source. Multiple data channels can be read at once from
23 * :file:`enable`, activate buffer capture.
35 is non *zero*, then a triggered capture will contain data samples for this
52 For example, a driver for a 3-axis accelerometer with 12 bit resolution where
53 data is stored in two 8-bits registers as follows::
56 +---+---+---+---+---+---+---+---+
58 +---+---+---+---+---+---+---+---+
61 +---+---+---+---+---+---+---+---+
63 +---+---+---+---+---+---+---+---+
[all …]
/Documentation/devicetree/bindings/timer/
Drenesas,rz-mtu3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/renesas,rz-mtu3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/G2L Multi-Function Timer Pulse Unit 3 (MTU3a)
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 This hardware block consists of eight 16-bit timer channels and one
14 32-bit timer channel. It supports the following specifications:
15 - Pulse input/output: 28 lines max
16 - Pulse input 3 lines
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/Documentation/devicetree/bindings/dma/
Dloongson,ls1b-apbdma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/loongson,ls1b-apbdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson-1 APB DMA Controller
10 - Keguang Zhang <keguang.zhang@gmail.com>
13 Loongson-1 APB DMA controller provides 3 independent channels for
14 peripherals such as NAND, audio playback and capture.
19 - const: loongson,ls1b-apbdma
20 - items:
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/Documentation/iio/
Diio_devbuf.rst1 .. SPDX-License-Identifier: GPL-2.0
10 The Industrial I/O core offers a way for continuous data capture based on a
11 trigger source. Multiple data channels can be read at once from
14 Devices with buffer support feature an additional sub-directory in the
25 ----------
31 ----------
33 Read / Write attribute which starts / stops the buffer capture. This file should
34 be written last, after length and selection of scan elements. Writing a non-zero
36 combination of channels is given.
39 -------------
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/Documentation/sound/soc/
Dcodec-to-codec.rst9 --------- ---------
11 CPU -------> codec
13 --------- ---------
18 ---------
20 codec-2
22 ---------
24 dai-2
26 ---------- ---------
27 | | dai-1 | |
28 CPU -------> codec-1
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Dclocking.rst10 ------------
15 audio playback and capture sample rates.
23 ----------
32 Bit Clock can be generated as follows:-
34 - BCLK = MCLK / x, or
35 - BCLK = LRC * x, or
36 - BCLK = LRC * Channels * Word Size
40 rate, number of channels and word size) to save on power.
/Documentation/driver-api/media/drivers/
Dpxa_camera.rst1 .. SPDX-License-Identifier: GPL-2.0
3 PXA-Camera Host Driver
9 -----------
18 ---------------------
26 capture. The new buffers are "appended" at the tail of the DMA chain, and
35 c) Capture global finite state machine schema
37 .. code-block:: none
39 +----+ +---+ +----+
42 +-----------+ +------------------------+
43 | STOP | | Wait for capture start |
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