Searched full:cascade (Results 1 – 17 of 17) sorted by relevance
13 and Ethernet PHYs to drive some bytes of the cascade automatically.39 shift register cascade.47 in the shift register cascade.54 The dsl core can control the 2 LSBs of the gpio cascade. This 2 bit68 The gphy core can control 3 bits of the gpio cascade. In the xRX200 family
20 shift register cascade.
18 - cascade pattern19 - inversed cascade pattern
12 Example for mips when used in cascade mode:
14 platforms internal interrupt controller cascade.
55 2 ISA cascade79 2 ISA cascade
15 This implementation supports only cascade mode.
39 - Cascade connection operation available76 MTU1 and MTU2 operate independently, and cascade connection 32-bit phase
10 The Parametric Equalizer (PEQ) is a cascade of biquad filters with
23 errors to cascade after the initial failure, hiding the original failure
20 - Cascade Lake generation - (Parts affected by ITS guest/host separation)
30 Cascade mode for Pipe LED::58 Inverted cascade mode for Pipe LED::
140 - interrupts : should contain the cascade interrupt of the "flipper" pic
30 2: 0 XT-PIC cascade
146 mechanism to make the freeze state cascade to "companion" PEs but
769 2: 0 XT-PIC cascade789 2: 0 0 XT-PIC cascade
815 DSA (cascade) and CPU ports are also called "shared" ports because they service