Searched +full:cci +full:- +full:control +full:- +full:port (Results 1 – 11 of 11) sorted by relevance
| /Documentation/devicetree/bindings/arm/ |
| D | arm,cci-400.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/arm/arm,cci-400.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: ARM CCI Cache Coherent Interconnect 10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 13 ARM multi-cluster systems maintain intra-cluster coherency through a cache 14 coherent interconnect (CCI) that is capable of monitoring bus transactions 18 clusters, through memory mapped interface, with a global control register 19 space and multiple sets of interface control registers, one per slave [all …]
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| D | cci-control-port.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/arm/cci-control-port.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: CCI Interconnect Bus Masters 10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 13 Masters in the device tree connected to a CCI port (inclusive of CPUs 19 cci-control-port: 25 - | 27 #address-cells = <1>; [all …]
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| D | cpus.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> 21 with updates for 32-bit and 64-bit ARM systems provided in this document. 30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in 59 On 32-bit ARM v7 or later systems this property is 68 On ARM v8 64-bit systems this property is required 71 * If cpus node's #address-cells property is set to 2 79 * If cpus node's #address-cells property is set to 1 [all …]
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| /Documentation/devicetree/bindings/i2c/ |
| D | qcom,i2c-cci.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/i2c/qcom,i2c-cci.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Qualcomm Camera Control Interface (CCI) I2C controller 10 - Loic Poulain <loic.poulain@linaro.org> 11 - Robert Foss <robert.foss@linaro.org> 16 - enum: 17 - qcom,msm8226-cci 18 - qcom,msm8974-cci [all …]
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | ovti,ov5647.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Dave Stevenson <dave.stevenson@raspberrypi.com> 11 - Jacopo Mondi <jacopo@jmondi.org> 13 description: |- 14 The OV5647 is a raw image sensor with MIPI CSI-2 and CCP2 image data 15 interfaces and CCI (I2C compatible) control bus. 29 pwdn-gpios: 33 port: [all …]
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| D | samsung,s5k6a3.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 13 S5K6A3(YX) is a raw image sensor with MIPI CSI-2 and CCP2 image data 14 interfaces and CCI (I2C compatible) control bus. 26 clock-names: 28 - const: extclk 30 clock-frequency: 38 afvdd-supply: [all …]
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| D | galaxycore,gc05a2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: GalaxyCore gc05a2 1/5" 5M Pixel MIPI CSI-2 sensor 11 - Zhi Mao <zhi.mao@mediatek.com> 14 The gc05a2 is a raw image sensor with an MIPI CSI-2 image data 15 interface and CCI (I2C compatible) control bus. The output format 28 dovdd-supply: true 30 avdd-supply: true 32 dvdd-supply: true [all …]
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| D | galaxycore,gc08a3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: GalaxyCore gc08a3 1/4" 8M Pixel MIPI CSI-2 sensor 11 - Zhi Mao <zhi.mao@mediatek.com> 14 The gc08a3 is a raw image sensor with an MIPI CSI-2 image data 15 interface and CCI (I2C compatible) control bus. The output format 28 dovdd-supply: true 30 avdd-supply: true 32 dvdd-supply: true [all …]
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| D | hynix,hi846.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: SK Hynix Hi-846 1/4" 8M Pixel MIPI CSI-2 sensor 10 - Martin Kepplinger <martin.kepplinger@puri.sm> 12 description: |- 13 The Hi-846 is a raw image sensor with an MIPI CSI-2 image data 14 interface and CCI (I2C compatible) control bus. The output format 18 - $ref: /schemas/media/video-interface-devices.yaml# 29 - description: Reference to the mclk clock. [all …]
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| /Documentation/devicetree/bindings/net/ |
| D | mediatek,net.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Lorenzo Bianconi <lorenzo@kernel.org> 11 - Felix Fietkau <nbd@nbd.name> 20 - mediatek,mt2701-eth 21 - mediatek,mt7623-eth 22 - mediatek,mt7621-eth 23 - mediatek,mt7622-eth 24 - mediatek,mt7629-eth [all …]
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| /Documentation/driver-api/cxl/ |
| D | maturity-map.rst | 1 .. SPDX-License-Identifier: GPL-2.0 9 <https://computeexpresslink.org/cxl-specification-landing-page>`_ that 14 <https://lore.kernel.org/linux-cxl/?q=s%3APULL+s%3ACXL+tc%3Atorvalds+NOT+s%3ARe>`_, 20 the change-history of this document provides an overview summary of the 25 - [3] Mature: Work in this area is complete and no changes on the horizon. 29 - [2] Stabilizing: Major functionality operational, common cases are 32 - [1] Initial: Capability that has exited the Proof of Concept phase, but 36 - [0] Known gap: Feature is on a medium to long term horizon to 39 the linux-cxl@vger.kernel.org community has started to look at it. 41 - X: Out of scope for kernel enabling, or kernel enabling not required [all …]
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