Searched full:cci (Results 1 – 23 of 23) sorted by relevance
| /Documentation/devicetree/bindings/i2c/ |
| D | qcom,i2c-cci.yaml | 4 $id: http://devicetree.org/schemas/i2c/qcom,i2c-cci.yaml#
7 title: Qualcomm Camera Control Interface (CCI) I2C controller
17 - qcom,msm8226-cci
18 - qcom,msm8974-cci
19 - qcom,msm8996-cci
23 - qcom,msm8916-cci
24 - const: qcom,msm8226-cci # CCI v1
28 - qcom,sc7280-cci
29 - qcom,sc8280xp-cci
30 - qcom,sdm845-cci
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| /Documentation/devicetree/bindings/arm/ |
| D | arm,cci-400.yaml | 4 $id: http://devicetree.org/schemas/arm/arm,cci-400.yaml#
7 title: ARM CCI Cache Coherent Interconnect
14 coherent interconnect (CCI) that is capable of monitoring bus transactions
24 pattern: "^cci(@[0-9a-f]+)?$"
28 - arm,cci-400
29 - arm,cci-500
30 - arm,cci-550
35 Specifies base physical address of CCI control registers common to all
48 const: arm,cci-400-ctrl-if
71 - const: arm,cci-400-pmu,r0
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| D | cci-control-port.yaml | 4 $id: http://devicetree.org/schemas/arm/cci-control-port.yaml#
7 title: CCI Interconnect Bus Masters
13 Masters in the device tree connected to a CCI port (inclusive of CPUs
19 cci-control-port:
33 cci-control-port = <&cci_control1>;
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| D | cpus.yaml | 282 cci-control-port: true
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| /Documentation/devicetree/bindings/interconnect/ |
| D | mediatek,cci.yaml | 4 $id: http://devicetree.org/schemas/interconnect/mediatek,cci.yaml#
7 title: MediaTek Cache Coherent Interconnect (CCI) frequency and voltage scaling
14 MediaTek Cache Coherent Interconnect (CCI) is a hardware engine used by
21 - mediatek,mt8183-cci
22 - mediatek,mt8186-cci
35 - const: cci
44 Phandle of the regulator for CCI that provides the supply voltage.
48 Phandle of the regulator for sram of CCI that provides the supply
66 cci: cci {
67 compatible = "mediatek,mt8183-cci";
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| /Documentation/driver-api/media/ |
| D | v4l2-cci.rst | 3 V4L2 CCI kAPI
5 .. kernel-doc:: include/media/v4l2-cci.h
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| D | v4l2-core.rst | 24 v4l2-cci
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| /Documentation/devicetree/bindings/cpufreq/ |
| D | cpufreq-mediatek.txt | 23 - mediatek,cci:
24 Used to confirm the link status between cpufreq and mediatek cci. Because
25 cpufreq and mediatek cci could share the same regulator in some MediaTek SoCs.
27 property to make sure mediatek cci is ready.
28 For details of mediatek cci, please refer to
29 Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
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| /Documentation/devicetree/bindings/clock/ |
| D | qcom,hfpll.yaml | 22 - qcom,msm8976-hfpll-cci
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| D | samsung,exynos7885-clock.yaml | 82 - description: CCI clock (from CMU_TOP)
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| D | samsung,exynos850-clock.yaml | 145 - description: CCI clock (from CMU_TOP)
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | ovti,ov5647.yaml | 15 interfaces and CCI (I2C compatible) control bus.
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| D | samsung,s5k6a3.yaml | 14 interfaces and CCI (I2C compatible) control bus.
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| D | galaxycore,gc05a2.yaml | 15 interface and CCI (I2C compatible) control bus. The output format
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| D | galaxycore,gc08a3.yaml | 15 interface and CCI (I2C compatible) control bus. The output format
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| D | hynix,hi846.yaml | 14 interface and CCI (I2C compatible) control bus. The output format
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | mediatek,mtk-cirq.yaml | 14 work outside of MCUSYS which comprises with Cortex-Ax cores, CCI and GIC.
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| /Documentation/devicetree/bindings/soc/mediatek/ |
| D | mtk-svs.yaml | 17 different power domains(CPU/GPU/CCI) according to
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | qcom,sm4450-tlmm.yaml | 76 cci_async_in0, cci_i2c, cci, cmu_rng, coex_uart1_rx,
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| /Documentation/devicetree/bindings/net/ |
| D | mediatek,net.yaml | 62 cci-control-port: true
448 cci-control-port = <&cci_control2>;
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| /Documentation/driver-api/cxl/ |
| D | maturity-map.rst | 130 * [0] Switch CCI
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| /Documentation/devicetree/bindings/soc/rockchip/ |
| D | grf.yaml | 24 - rockchip,rk3576-cci-grf
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| /Documentation/driver-api/media/drivers/ccs/ |
| D | mk-ccs-regs | 95 #include <media/v4l2-cci.h>
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