Searched +full:ce4100 +full:- +full:lapic (Results 1 – 2 of 2) sorted by relevance
| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | intel,ce4100-lapic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Local Advanced Programmable Interrupt Controller (LAPIC)
10 - Rahul Tanwar <rtanwar@maxlinear.com>
15 architecture design, with a local component (LAPIC) integrated
17 (lapic) receives interrupts from the processor's interrupt pins,
22 Many of the Intel's generic devices like hpet, ioapic, lapic have
23 the ce4100 name in their compatible property names because they
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| D | intel,ce4100-ioapic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/intel,ce4100-ioapic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rahul Tanwar <rtanwar@maxlinear.com>
15 architecture design, with a local component (LAPIC) integrated
17 (lapic) receives interrupts from the processor's interrupt pins,
22 Many of the Intel's generic devices like hpet, ioapic, lapic have
23 the ce4100 name in their compatible property names because they
24 first appeared in CE4100 SoC.
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